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W6692 pci isdn s/t-controller publication release date: october 1998 - 1 - revision a1 table of contents- 1. general description ................................ ................................ ................................ ............. 5 2. features ................................ ................................ ................................ ................................ .... 5 3. pin configuration ................................ ................................ ................................ .................. 6 4. pin description ................................ ................................ ................................ ........................ 6 5. system diagram and applications ................................ ................................ .................... 9 6. block diagram ................................ ................................ ................................ ....................... 10 7. functional descriptions ................................ ................................ ................................ ... 11 7.1 main block functions ................................ ................................ ................................ ............................ 11 7.2 layer 1 functions descriptions ................................ ................................ ................................ ............. 12 7.2.1 s/t interface transmitter/receiver ................................ ................................ ................................ .. 12 7.2.2 receiver clock recovery and timing generation ................................ ................................ ............ 15 7.2.3 layer 1 activation/deactivation ................................ ................................ ................................ ....... 16 7.2.3.1 states descriptions and command/indication codes ................................ ................................ ................. 16 7.2.3.2 state transition diagrams ................................ ................................ ................................ ........................ 18 7.2.4 d channel access control ................................ ................................ ................................ ............... 21 7.2.5 frame alignment ................................ ................................ ................................ ............................ 21 7.2.5.1 fainfa_1fr ................................ ................................ ................................ ................................ ................ 22 7.2.5.2 fainfb_1fr ................................ ................................ ................................ ................................ ................ 22 7.2.5.3 fainfd_1fr ................................ ................................ ................................ ................................ ............... 22 7.2.5.4 fainfa_kfr ................................ ................................ ................................ ................................ ................ 23 7.2.5.5 fainfb_kfr ................................ ................................ ................................ ................................ ................ 24 7.2.5.6 fainfd_kfr ................................ ................................ ................................ ................................ ............... 24 7.2.5.7 faregain ................................ ................................ ................................ ................................ ................... 24 7.2.6 multiframe synchronization ................................ ................................ ................................ ............. 25 7.2.7 test functions ................................ ................................ ................................ ................................ 26 7.3 serial interface bus ................................ ................................ ................................ .............................. 27 7.4 b channel switching ................................ ................................ ................................ ............................. 28 7.5 pcm port ................................ ................................ ................................ ................................ .............. 28 7.6 d channel hdlc controller ................................ ................................ ................................ .................. 28 7.6.1 d channel message transfer modes ................................ ................................ ............................... 30 7.6.2 reception of frames in d channel ................................ ................................ ................................ .. 30 7.6.3 transmission of frames in d channel ................................ ................................ ............................. 31
W6692 - 2 - 7.7 b channel hdlc controller ................................ ................................ ................................ .................. 32 7.7.1 reception of frames in b channel ................................ ................................ ................................ .. 32 7.7.2 transmission of frames in b channel ................................ ................................ ............................. 33 7.8 gci mode serial interface bus ................................ ................................ ................................ ............. 34 7.8.1 gci mode c/i channel handling ................................ ................................ ................................ ..... 35 7.8.2 gci mode monitor channel handling ................................ ................................ .............................. 35 7.9 pci interface circuit ................................ ................................ ................................ .............................. 36 7.9.1 pci slave mode and configuration serial eeprom ................................ ................................ ........ 36 7.9.2 cascade structure of interrupt sources ................................ ................................ ........................... 39 7.10 peripheral control ................................ ................................ ................................ ............................... 41 8. register descriptions ................................ ................................ ................................ ....... 42 8.1 chip control and d_ch hdlc controller ................................ ................................ ............................... 42 8.1.1 d_ch receive fifo d_rfifo read address 00h ................................ ................................ ............ 44 8.1.2 d_ch transmit fifo d_xfifo write address 04h ................................ ................................ ........... 44 8.1.3 d_ch command register d_cmdr write address 08h ................................ ................................ .... 44 8.1.4 d_ch mode register d_mode read/write address 0ch ................................ ................................ 45 8.1.5 d_ch timer register d_timr read/write address 10h ................................ ................................ .. 46 8.1.6 interrupt status register ista read_clear address 14h ................................ ............................... 46 8.1.7 interrupt mask register imask r/w address 18h ................................ ................................ ........... 48 8.1.8 d_ch extended interrupt register d_exir read_clear address 1ch ................................ ............... 48 8.1.9 d_ch extended interrupt mask register d_exim read/write address 20h ................................ ...... 49 8.1.10 d_ch status register d_star read address 24h ................................ ................................ ...... 49 8.1.11 d_ch receive status register d_rsta read address 28h ................................ .......................... 50 8.1.12 d_ch sapi address mask d_sam read/write address 2ch ................................ ........................ 50 8.1.13 d_ch sapi1 register d_sap1 read/write address 30h ................................ .............................. 50 8.1.14 d_ch sapi2 register d_sap2 read/write address 34h ................................ ............................... 51 8.1.15 d_ch tei address mask d_tam read/write address 38h ................................ ........................... 51 8.1.16 d_ch tei1 register d_tei1 read/write address 3ch ................................ ................................ . 51 8.1.17 d_ch tei2 register d_tei2 read/write address 40h ................................ ................................ .. 51 8.1.18 d_ch receive frame byte count high d_rbch read address 44h ................................ ............. 52 8.1.19 d_ch receive frame byte count low d_rbcl read address 48h ................................ .............. 52 8.1.20 timer 2 timr2 write address 4ch ................................ ................................ ................. 52 8.1.21 layer 1_ready code l1_rc read/write address 50h ................................ ...................... 53 8.1.22 d_ch control register d_ctl read/write address 54h ................................ ................................ 53 8.1.23 command/indication receive register cir read address 58h ................................ .................... 54 8.1.24 command/indication transmit register cix write address 5ch ................................ .................. 55
W6692 publication release date: october 1998 - 3 - revision a1 8.1.25 s/q channel receive register sqr read address 60h ................................ .............................. 55 8.1.26 s/q channel transmit register sqx write address 64h ................................ ............................. 56 8.1.27 peripheral control register pctl read/write address 68h ................................ ......................... 56 8.1.28 monitor receive channel mor read address 6ch ................................ ................................ ..... 57 8.1.29 monitor transmit channel mox read/write address 70h ................................ ........................... 58 8.1.30 monitor channel status register mosr read_clear address 74h ................................ ......... 58 8.1.31 monitor channel control register mocr read/write address 78h ................................ . 58 8.1.32 gci mode control register gcr read/write address 7ch ................................ ................ 59 8.1.33 peripheral address register xaddr read/write address f4h ................................ .................... 60 8.1.34 peripheral data register xdata read/write address f8h ................................ ................... 61 8.1.35 serial eeprom control register epctl write address 68h ................................ ....................... 62 8.2 b1 hdlc controler ................................ ................................ ................................ ............................... 62 8.2.1 b1_ch receive fifo b1_rfifo read address 80h ................................ ................................ ........ 63 8.2.2 b1_ch transmit fifo b1_xfifo write address 84h ................................ ................................ .... 63 8.2.3 b1_ch command register b1_cmdr write address 88h ................................ ............................... 63 8.2.4 b1_ch mode register b1_mode read/write address 8ch ................................ ............................ 64 8.2.5 b1_ch extended interrupt register b1_exir read_clear address 90h ................................ ............ 66 8.2.6 b1_ch extended interrupt mask register b1_exim read/write address 94h .................. 66 8.2.7 b1_ch status register b1_star read address 98h ................................ ............................... 66 8.2.8 b1_ch address mask register 1 b1_adm1 read/write address 9ch ................................ ............. 67 8.2.9 b1_ch address mask register 2 b1_adm2 read/write address a0h ................................ ............. 67 8.2.10 b1_ch address register 1 b1_adr1 read/write address a4h ................................ ............. 68 8.2.11 b1_ch address register 2 b1_adr2 read/write address a8h ................................ .................... 68 8.2.12 b1_ch receive frame byte count low b1_rbcl read address ach ................................ ........... 68 8.2.13 b1_ch receive frame byte count high b1_rbch read address b0h ................................ .......... 68 8.3 b2 hdlc controller ................................ ................................ ................................ ............................... 69 8.4 pci configuration register ................................ ................................ ................................ ................... 70 8.4.1 device/vendor id register read address 00 h ................................ ................................ ............... 71 8.4.2 status/command register read/write address 04 h ................................ ................................ ...... 71 8.4.3 class code/revision id register read address 08 h ................................ ................................ .... 73 8.4.4 header type/latency timer register read address 0c h ................................ .............................. 74 8.4.5 base address register 0 read/write address 10 h ................................ ................................ ....... 74 8.4.6 base address register 1 read/write address 14 h ................................ ................................ ......... 76 8.4.7 subsystem/subsystem vendor id register read address 2c h ................................ ....................... 76 8.4.8 interrupt line register read/write address 3c h ................................ ................................ .......... 77
W6692 - 4 - 9. electrical characteristics ................................ ................................ ............................. 77 9.1 absolute maximum rating ................................ ................................ ................................ .................... 77 9.2 power supply ................................ ................................ ................................ ................................ ....... 78 9.3 dc characteristics ................................ ................................ ................................ ................................ 78 9.4 preliminary switching characteristics ................................ ................................ ................................ ... 80 9.4.1 pcm interface timing ................................ ................................ ................................ ..................... 80 9.4.2 serial eeprom timing ................................ ................................ ................................ ................... 81 9.4.3 peripheral interface timing ................................ ................................ ................................ ............. 82 9.5 ac timing test conditions ................................ ................................ ................................ ................... 83 10. package dimensions ................................ ................................ ................................ .......... 83
W6692 publication release date: october 1998 - 5 - revision a1 1. general description the winbond ' s single chip pci bus isdn s/t interface controller (W6692) is an all-in-one device suitable for isdn internet access. three hdlc controllers are incorporated in the chip, one for d channel and the other two for b channels. these hdlc controllers facilitate efficient access to signalling and data services. the pcm codec interface provides voice service or other services. the built in pci 2.1 interface circuit makes glueless design for pci bus add-on card application. 2. features full duplex 2b + d s/t-interface transceiver compatible with itu-t i.430 recommendation - four wire operation - received clock recovery - layer 1 activation/deactivation procedures - d channel access control - supports multiframe synchronization supports lapd protocol - flag generation/recognition - bit stuffing (zero insertion/deletion) - frame check sequence (fcs) generation/check - maskable address recognition - fifo buffer (2 128 bytes) two b channel hdlc controllers - maskable address recognition - bit rate options: 56 or 64 kbps - transparent (hdlc mode) or extended transparent mode (clear channel) - fifo buffer (2 128 bytes) per b channel two pcm codec interfaces for speech and pots application various b channel switching capabilities gci interface fo r connection with u transceiver built in pci 2.1 slave mode circuit serial eeprom interface for pci configuration timer, interrupt input, io/microprocessor interface for pots or other peripheral control +5 volt power supply advanced cmos technology low power consumption packaged in 100-pin qfp
W6692 - 6 - 3. pin configuration W6692 isdn-pci 1 2 3 7 4 5 6 1 1 8 9 1 0 1 3 1 2 1 7 1 4 1 5 1 6 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 5 8 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5 1 5 2 5 3 5 4 5 5 5 6 5 7 6 0 5 9 6 1 8 0 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 81 88 82 83 84 85 86 87 89 100 90 91 92 93 94 95 96 97 98 99 i o 3 / x a d 3 p e r r # x t a l 2 i o 6 / x a d 6 c / b e 1 # p a r d e v s e l # v d d d f r a m e # t o u t 2 v d d d s t o p # v s s d t r d y # i r d y # a d 1 7 c / b e 2 # a d 1 6 a d 1 8 a d 1 9 v d d b v s s b ad29 ad24 ad25 ad26 clk ad27 ad28 vddb ad30 vssb ad31 vddd vssd vssb ad9 ad8 c/be0# ad7 ad6 vssb ad5 vddb ad3 ad2 ad4 t r s t v d d d v s s d x t a l 1 p f c k 1 p b c k t e s t p p f c k 2 ad0 ad1 i o 8 / x a l e p t x d d i n d o u t v s s d s x 1 s x 2 p r x d v d d a x i n t i n 1 x i n t i n 0 rst# f s c e p s d i e p s d o ad10 ad11 vddb a d 1 3 a d 1 4 i o 2 / x a d 2 i o 1 / x a d 1 i o 0 / x a d 0 i o 4 / x a d 4 i o 5 / x a d 5 i o 7 / x a d 7 a d 1 2 a d 1 5 sr1 vssa sr2 e p c s d c l e p s k i o 9 / x r d b i o 1 0 / x w r b i n t a # c/be3# idsel ad23 ad22 ad21 ad20 figure 3.1 4. pin description table 4.1 W6692 pin descriptions notation: the suffix " # " indicates an active low signal. pin name pin no. type functions pci bus ad31-ad0 85, 86, 87, 90, 91, 92, 93, 94, 97, 98, 99, 100, 7, 8, 9, 10, 23, 24, 25, 30, 33, 34, 35, 36, 38, 39, 40, 41, 44, 45, 46, 47 i/o address and data are multiplexed on the same pci pins. during the address phase, ad31-0 contain a 32-bit physical address. during the data phase, ad7-ad0 contain the least significant byte and ad31-ad24 contain the most significant byte. c/be3#-c/be0# 95, 11, 22, 37 i bus command and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, c/be3#-c/be0# define the bus command. during data phase, c/be3#-c/be0# are used as byte enable.
W6692 publication release date: october 1998 - 7 - revision a1 pin description, contiuned pin name pin no. type functions par 21 i/o parity is even parity across ad31-ad0 and c/be3#- c/be0#. frame# 12 i frame# is asserted to indicate a bus transaction is beginning. pci bus trdy# 14 o target ready indicates W6692 is able to complete the current data phase of the transaction. irdy# 13 i initiator ready indicates the bus master s ability to complete the current data phase of the transaction. stop# 18 o stop indicates W6692 is requesting the master to stop the current transaction. devsel# 15 o device select indicates W6692 has decoded its address as the target of the current access. idsel 96 i initialization device select is used as chip select during configuration read and write transactions. perr# 19 o parity error is only for the reporting of data parity errors. clk 84 i pci clock. all other pci signals, except rst#, inta# are sampled on the rising edge of clk. rst# 81 i pci reset. rst# may be asynchronous to clk when asserted or deasserted. inta# 80 o interrupt. this is level sensitive, active low and open drain output. gci bus dcl 72 i gci bus data clock of the frequency: 1.536 mhz. fsc 71 i gci bus frame synchronization clock: 8 khz. din 70 i gci bus data port 0 (ex: must be connectted to siemens peb2091's dout pin). dout 69 o gci bus data port 1 (ex: must be connectted to siemens peb2091's din pin) pcm bus pfck1 64 o pcm port 1 frame synchronization signal, with 8 khz repetition rate and 8 bit pulse width. pfck2 62 o pcm port 2 frame synchronization signal, with 8 khz repetition rate and 8 bit pulse width. pbck 63 o pcm bit synchronization clock of 1.536 mhz. ptxd 65 o pcm transmit data output. a maximum of two channels with 64 kbit/s data rate can be multiplexed on this signal.
W6692 - 8 - pin description, contiuned pin name pin no. type functions prxd 66 i pcm receive data input. a maximum of two channels with 64 kbit/s data rate can be multiplexed on this signal. isdn signals and external crystal sr1 49 i s/t bus receiver input (negative). sr2 50 i s/t bus receiver input (positive). sx1 54 o s/t bus transmitter output (positive). sx2 55 o s/t bus transmitter output (negative). xtal1 56 i crystal or oscillator clock input. the clock frequency: 7.68 mhz 100ppm. xtal2 57 o crystal clock output. left unconnected when using oscillator. external eeprom interface epcs 73 o serial eeprom chip select (active high). epsk 74 o serial eeprom data clock (clock frequency < 250 khz). epsdi 76 i serial eeprom data input (must be connected to external eeprom's data output). epsdo 75 o serial eeprom data output (must be connected to external eeprom's data input). functional test testp 61 i used to enable normal operation (1) or enter test mode (0). trst 60 o if terminal equipment function is enabled, the reset pulse width is: - 125 us when generated by the watchdog timer. - 16 ms when generated by exchange awake indication code change. peripheral control tout2 20 o timer 2 output. a square wave with 50% duty cycle, 2 - 126 ms period can be generated. xintin0 52 i a level change (either direction) will generate a maskable interrupt on the pci bus interrupt request pin inta#. xintin1 53 i a level change (either direction) will generate a maskable interrupt on the pci bus interrupt request pin inta#.
W6692 publication release date: october 1998 - 9 - revision a1 pin description, contiuned pin name pin no. type functions io0-io10 79, 78, 77, 29, 28, 27, 26, 4, 3, 2, 1 i/o when confiured as simple io mode (pctl: xmode = 0), these pins can read/write data from/to peripheral components. the pin directions are selected via register. xad7-xad0 29, 28, 27, 26, 4, 3, 2, 1 i/o when configured as microprocessor mode (pctl: xmode = 1), address and data are multiplexed on these pins. xale 77 o when configured as microprocessor mode (pctl: xmode = 1), this is the address latch enable output. xrdb 78 o when configured as microprocessor mode (pctl: xmode = 1), this is the read pulse. xwrb 79 o when configured as microprocessor mode (pctl: xmode = 1), this is the write pulse. power and ground vddd 17, 58, 67, 83 i digital power supply (5v 5%). vdda 51 i analog power supply (5v 5%). vddb 6, 32, 43, 89 i pci bus power supply. vssd 16, 59, 68, 82 i digital ground. vssa 48 i analog ground. vssb 5, 31, 42, 88 i pci bus ground. 5. system diagram and applications typical applications include: - pci passive s-card for data only service - pci passive s-card with one handset/pots connection - pci passive s-card with two pots connections the all-in-one characteristic of W6692 makes it excellent for isdn internet-access passive card applications. the booming home pc market and powerful cpu capability make it possible to make a very low-cost isdn internet access card by using cpu's computing power and user friendly pci interface. W6692 is designed for this type of scenario. W6692 integrates three hdlc controllers in the chip and interfaces to pci bus directly. in addition, W6692 provides peripheral control circuits for pcm codec and pots interface. in the first and second applications, the all-in-one feature of W6692 makes glue circuit unnecessary. in the third application, only a few ttl-like glue circuits are needed for the two pots interface control.
W6692 - 10 - transformer module W6692 pci s-controller pcm codec x2 4-wire s/t eeprom pots circuit x2 protection circuit nt phone fax figure 5.1 isdn internet passive s-card with two pots connections 6. block diagram the block diagram of W6692 is shown in figure 6.1 b-channel switching pci bus d b1 b2 line transceiver & ami/bin conversion gci circuit 4-wire s/t 2b+d serial interface bus (sib) 2b+d d hdlc controller b1 hdlc controller b2 hdlc controller fifo fifo fifo pcm port pcm codec pci interface circuit gci bus dpll and timing generator crystal/oscillator (7.68 mhz) peripheral control pots circuit figure 6.1 W6692 functional block diagram
W6692 publication release date: october 1998 - 11 - revision a1 7. functional descriptions 7.1 main block functions the functional block diagram of W6692 is shown in figure 6.1. the main function blocks are: - layer 1 function according to itu-t i.430 - serial interface bus (sib) - b channel switching - supports gci bus interface - pcm port (x 2) - d channel hdlc controller - b channel hdlc controllers (x 2) - pci interface circuit - peripheral control the layer 1 function includes: - s/t bus transmitter/receiver - timing recovery using digital phase locked loop (dpll) circuit - layer 1 activation/deactivation - d channel access control - frame alignment - multiframe synchronization - test functions the serial interface bus performs the multiplexing/demultiplexing of d and 2b channels. the b channel switching determines the connection between layer1/gci, layer 2 and pcm. the gci circuit is used to connect a u transceiver. in this case, the layer 1 function of s/t interface is disabled. after power up or reset, the gci circuit is disabled and the s/t layer 1 function is enabled. the pcm port provides two 64 kbps clear channels to connect to pcm codec chips. the d channel hdlc controller performs the lapd (link access procedure on the d channel) protocol according to itu-t i.441/q.921 recommendation. there are two independent b channel hdlc controllers. they can be used to support hdlc-like protocols such as internet ppp. the pci interface circuit implements pci specification revision 2.1 slave mode function. the peripheral control block is used to control other peripheral devices such as codec, pots, leds or device with microprocessor interface.
W6692 - 12 - 7.2 layer 1 functions descriptions the layer 1 functions includes: - transmitter/receiver which conform to the electrical specifications of itu-t i.430 - receiver clock recovery and timing generation - output phase delay (deviation) compensation - layer 1 activation/deactivation procedures - d channel access control - frame alignment - multiframe synchronization - test functions 7.2.1 s/t interface transmitter/receiver according to itu-t i.430, pseudo-ternary code with 100% pulse width is used in both directions of transmission on the s/t interface. the binary "1" is represented by no line signal (zero volt), whereas a binary "0" is represented by a positive or negative pulse. data transmissions on the s/t interface are arranged as frame structures. the frame is 250 m s long and consists of 48 bits, which corresponds to a 192 kbit/s line rate. each frame carries two octets of b1 channel, two octets of b2 channel and four d channel bits. therefore, the 2b+d data rate is 144 kbit/s. the frame structure is shown in figure 7.1. the frame begin is marked by a framing bit, which is followed by a dc balancing bit. the first binary "0" following the framing bit balancing bit is of the same polarity as the framing bit balancing bit, and subsequent binary zeros must alternate in polarity.
W6692 publication release date: october 1998 - 13 - revision a1 figure 7.1 frame structure at s/t interface there are three wiring configurations according to i.430: point-to-point, short passive bus and extended pass bus. they are shown in figure 7.2. d l f l b 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 e d a f a n b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 e d mb 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 e d s b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 e 0 1 0 nt ? te d l f l b 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 l d l f a l b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 l d l b 1 b 1 b 1 b 1 b 1 b 1 b 1 b 1 l d l b 2 b 2 b 2 b 2 b 2 b 2 b 2 b 2 l d l f l 0 1 0 te ? nt 48 bits in 250 m s 2 bits f = framing bit l = dc balancing bit d = d channel bit e = d channel echo bit f a = auxiliary framing bit or q- bit n = bit set to a binary value n=f a b1 = bit within b channel 1 b2 = bit within b channel 2 a = bit used for activation s = bit used for s channel m = multiframe bit
W6692 - 14 - figure 7.2 W6692 wiring configuration in te applications the transmitter and receiver are implemented by differential circuits to increase signal to noise ratio (snr). the nominal differential line pulse amplitude at 100 w termination is 750 mv, zero to peak. transformers with 2:1 turn ration are needed at transmitter and receiver for voltage level translation and dc isolation. to meet the electrical characteristic requirements in i.430, some additional circuits are needed. at the transmitter side, the external resistors (18 to 33 w ) are used to adjust the output pulse amplitude and to meet the transmitter active impedance ( 3 20 w when transmitting binary zeros). at the receiver side, the 1.8 k w resistors protect the device inputs, while the 10 k w resistors (1.8 k w +8.2 k w ) limit the peak current in impedance tests. the diode bridge is used for overvoltage protection. w669 te tr tr nt 1000 m (a) point-to-point configuration tr tr nt 100~200 m (b) short passive bus configuration w669 te1 w669 te8 . . . . . 10m tr tr nt 100~200 m (c) extended passive bus configuration w669 te1 w669 te8 . . . . 10m 50m tr: terminating
W6692 publication release date: october 1998 - 15 - revision a1 figure 7.3 external transmitter circuitry figure 7.4 external receiver circuitry after hardware reset, the receiver may enter power down state to save power. in thist state, the internal clocks are turned off, but the analog level detector is still active to detect signal coming from the s interface. the power down state is left either by non-info 0 signal from s interface or c/i command from micro-processor. 7.2.2 receiver clock recovery and timing generation a digital phase locked loop (dpll) circuit is used to derive the receive clock from the received data stream. this dpll uses a 7.68 mhz clock as reference. according to i.430, the transmit clock is normally delayed by 2 bit time from the receive clock. the "total phase deviation input to output" is - 7% to +15% of a bit period. in some cases, delay compensation may be needed to meet this requirement (see ops1-0 bits in d_ctl register). sx1 sx2 18-33 w 18-33 w gnd o v dd 2:1 100 w sr1 sr2 1.8 k w 1.8 k w gnd o v dd 8.2 k w 8.2 k w 2:1 100 w
W6692 - 16 - table 7.1 output phase delay compensation table ops1 ops0 effect 0 0 no phase delay compensation 0 1 phase delay compensation 260 ns 1 0 phase delay compensation 520 ns 1 1 phase delay compensation 1040 ns W6692 does not need rc filter on receiver side, therefore zero delay compensation is selected normally. this is the default setting. the pcm output clocks (pfck1-2, pbck) are synchronous to the s-interface timing. 7.2.3 layer 1 activation/deactivation the layer 1 activation/deactivation procedures are implemented by a finite state machine. the state transitions are triggered by signals received at s interface or commands issued from micro-processor. the state outputs signals to s interface and indication to micro-processor. the cix register is used by micro-processor to issue command, and the cir register is used by micro-processor to receive indication. some commands are used for special purposes. they are "layer 1 reset", "analog loopback", "send continuous zeros" and "send single zero". 7.2.3.1 states descriptions and command/indication codes f3 deactivated without clock this is the "deactivated" state of itu-t i.430. the receive line awake unit is active except during a hardware reset pulse. after reset, once the indication "1111" has been read out, internal clocks will turn off and stay at this state if info 0 is received on the s line. the turn off time is approximate 93 ms. the command eck must be issued to activate the clocks. f3 deactivated with clock this state is identical to "f3 deactivated without clock" except the internal clocks are enabled. the state is entered by a eck command. the clocks are enabled approximately 0.5 ms to 4 ms after the eck command, depending on the crystal capacitances. (it is about 0.5 ms for 12 to 33 pf capacitance). f3 awaiting deactivation the W6692 enters this state after receiving info 0 (in states f5 to f8) for 16 ms (64 frames). this time constant prevents spurious effect on s interface. any non-info 0 signal on the s interface causes transition to "f5 identifying input" state. if this transition does not occur in a specific time (500 - 1000 ms), the micro-processor may issue drc or eck command to deactivate layer 1. f4 awaiting signal this state is reached when an activate request command has been received. in this state, the layer 1 transmits info1 and info 0 is received from the s interface. the software starts timer t3 of i.430
W6692 publication release date: october 1998 - 17 - revision a1 when issuing activate request command. the software deactivates layer 1 if no signal other than info 0 has been received on s interface before expiration of t3. f5 identifying input after the receipt of any non-info 0 signal from nt, the W6692 ceases to transmit info 1 and awaits identification of info 2 or info 4. this state is reached at most 50 m s after a signal different from info 0 is present at the receiver of the s interface. f6 synchronized when W6692 receives an activation signal (info 2), it responds with info 3 and waits for normal frames (info 4). this state is reached at most 6 ms after an info 2 arrives at the s interface (in case the clocks were disabled in "f3 deactivated without clock"). f7 activated this is the normal active state with the layer 1 protocol activated in both directions. from state "f6 synchronized" , state f7 is reached at most 0.5 ms after reception of info 4. from state "f3 deactivated without clock" with the clocks disabled, state f7 is reached at most 6 ms after the W6692 is directly activated by info 4. f8 lost framing this is the state where the W6692 has lost frame synchronization and is awaiting resynchronization by info 2 or info 4 or deactivation by info 0. special states: analog loop initiated on enable analog loop command, info 3 is sent by the line transmitter internally to the line receiver (info 0 is sent to the line). the receiver is not yet synchronized. analog loop activated the receiver is synchronized on info 3 which is looped back internally from the transmitter. the indication 'ti" or "ati" is sent depending on whether or not a signal different from info 0 is detected on the s interface. send continuous pulses a 96 khz continuous pulse with alternating polarities is sent. send single pulses a 2 khz isolated pulse with alternating polarities is sent. layer 1 reset a layer 1 reset command forces the transmission of info 0 and disables the s line awake detector. thus activation from nt is not possible. there is no indication in reset state. the reset state can be left only with eck command.
W6692 - 18 - table 7.2 layer 1 command codes command sym. code description enable clock eck 0000 enable internal clocks layer 1 reset rst 0001 layer 1 reset send continuous pulses scp 0100 send continuous pulses at 96 khz send single pulses ssp 0010 send isolated pulses at 2 khz activate request at priority 8 ar8 1000 activate layer 1 and set d channel priority level to 8 activate request at priority 10 ar10 1001 activate layer 1 and set d channel priority to 10 enable analog loopback eal 1010 enable analog loopback deactivate layer 1 drc 1111 deactivate layer 1 and disable internal clocks table 7.3 layer 1 indication codes indication sym. code descriptions clock enabled ce 0111 internal clocks are enabled deactivate request downstream drd 0000 deactivation request by s interface, i.e info 0 received level detected ld 0100 signal received, receiver not synchronous activate request downstream ard 1000 info 2 received test indication ti 1010 analog loopback activated or continuous zeros or single zeros transmitted awake test indication ati 1011 level detected during test function activate indication with priority class 1 ai8 1100 info 4 received, d channel priority is 8 or 9 activate indication with priority class 2 ai10 1101 info 4 received, d channel priority is 10 or 11 clock disabled cd 1111 layer 1 deactivated, internal clocks are disabled 7.2.3.2 state transition diagrams the followings are the state transition diagrams which implement the activation/deactivation state matrix in i.430 (table 5/i.430). the "command" and "s receive" entries in each state octagon keeps the state, the "indication" and "s transmit" entries in each state octagon are the state outputs. for example, at "f3 deactivated with clock" state, the layer 1 will stay at this state if the command is "eck" and the info 0 is received on s interface. at this state, it provides "ce" indication to the micro-processor and transmits info 0 on s interface. a "ar8/10" command causes transition to f4 and non-info 0 signal causes transition to f5. note that the command code writtern by the micro- processor in cix register and indication code written by layer 1 in cir register are transmitted repeatedly until a new code is written.
W6692 publication release date: october 1998 - 19 - revision a1 figure 7.5 layer 1 activation/deactivation state diagram - normal mode state com ind s receive s trans. f4 await. signal ar8/10 ce i0 i1 f5 ident. input ^rst 1) ld any 2) i0 f6 synchronized ^rst 1) ard i2 i3 f7 activated ar8/10 ai8/10 i4 i3 f8 lost framing ^rst 1) ld any 2) i0 f3 deact w/o clk drc cd i0 i0 f3 deact with clk eck ce i0 i0 f3 await. deact. ar8/10 drd i0 i0 notes: 1. "^rst" means "not layer 1 reset command". 2. "any" means any signal other than i0, which has not yet been determined. 3. "^i0" means any signal other than i0. notation: ar8/1 ar8/10 drc eck drc drc eck eck ^i0 3) ^i0 3) ^i0 3) ^i0 3) i0 i0 i0 i0 i2 i4 i2 i4 lost framing i4 i2 lost framing
W6692 - 20 - figure 7.6 layer 1 activation/deactivation state diagram - special mode state com ind s receive s trans. reset rst none ignored i0 send cont. pulses scp ti ignored ic 3) send sing. pulses ssp ti ignored is 4) ana. loop init. eal ce ignored i3 5) ana. loop act. eal ti/ati ignored i3 5) rst scp ssp eal eck y 2) y 2) y 2) y 2) i3 5) ^i3 5) notation: notes: 1. rst can be issued at any state, while scp, scz and eal can be issued only at f3 or f7. 2. y is one of the commands : eck, drc, rst. 3. continuous pulses at 96 khz. 4. isolated pulses at 2 khz. 5. the info 3 is transmitted internally only.
W6692 publication release date: october 1998 - 21 - revision a1 7.2.4 d channel access control the d channel access control includes collision detection and priority management. the collision detection is always enabled. the priority management procedure as specified in itu-t i.430 is fully implemented in W6692. a collision is detected if the transmitted d bit and the received echo bit do not match. when this occurs, d channel transmission is immediately stopped and the echo channel is monitored to attempt the next d channel access. the layer 1 module uses an internal signal to inform layer 2 module of the collision condition (drdy bit goes inactive in d_star register). there are two priority classes: class 1 and class 2. within each class, there are normal and lower priority levels. table 7.4 d priority classes normal level lower level priority class 1 8 9 priority class 2 10 11 the selection of priority class is via the ar8/ar10 command. the following table summarizes the commands/indications used for setting the priority classes: table 7.5 d priority commands/indications command sym. code remarks activate request, set priority 8 ar8 1000 activation command, set d channel priority to 8 activate request, set priority 10 ar10 1001 activation command, set d channel priority to 10 indication abbr. remarks activate indication with priority 8 ai8 1100 info 4 received, d channel priority is 8 or 9 activate indication with priority 10 ai10 1101 info 4 received, d channel priority is 10 or 11 7.2.5 frame alignment the following sections describe the behavior of W6692 in respect to the cts-2 conformance test procedures for frame alignment. please refer to etsi-tm3 appendix b1 for detailed descriptions.
W6692 - 22 - 7.2.5.1 fainfa_1fr this test checks if te does not lose frame alignment on receipt of one bad frame. the pattern for the bad frame is defined as ix_96 khz. this pattern consists of alternating pulses at 96 khz during the whole frame. info 4 info 4 info 4 info 3 info 3 info 3 info 3 device settings result W6692 none pass 7.2.5.2 fainfb_1fr this test checks if te does not lose frame alignment on receipt of one ix_i4noflag frame which has no framing and balancing bit. the following figure indicates one possible ix_i4noflag waveform. info 4 info 4 info 4 info 3 info 3 info 3 info 3 device settings result W6692 none pass 7.2.5.3 fainfd_1fr this test checks if te does not lose frame alignment on receipt of one ix-i4viol16 frame. the ix_i4viol16 frame remains at binary "1" until the first b2 bit which is bit position 16. the pulse sequences are: framing bit, balancing bit, b2 bit, m bit, s bit, balancing bit. the te should reflect the received f a bit (f a = "1") in the transmitted frame. ix_96 khz ix_i4noflag i4_basic
W6692 publication release date: october 1998 - 23 - revision a1 info 4 info 4 info 4 info 3 info 3 info 3 device settings result W6692 none pass 7.2.5.4 fainfa_kfr this is to test the number k of ix_96 khz frames necessary for loss of frame alignment. info 4 info 4 info 3 info 3 info 3 device settings result W6692 k = 2 pass f a = 1 i3_basic with f a = 1 ix_i4viol16 i3_sfal info 0 ix_96khz ix_96khz ix_96khz
W6692 - 24 - 7.2.5.5 fainfb_kfr this is to test the number k of ix_i4noflag frames necessary for loss of frame alignment. info 4 info 4 info 3 info 3 info 3 device settings result W6692 k = 2 pass 7.2.5.6 fainfd_kfr this is to test the number k of ix_i4noflag frames necessary for loss of frame alignment. info 4 info 4 info 3 info 3 device settings result W6692 k = 2 pass 7.2.5.7 faregain this is to test the number m of good frames necessary for regain of frame alignment. the te regains frame alignment at m+1 frame. ix_i4noflag i3_sfal info 0 i4-basic ix_i4noflag ix_i4noflag i3_sfal info 0 f a = 1 info 3 with fa = 1
W6692 publication release date: october 1998 - 25 - revision a1 the W6692 achieves synchronization after 5 frames, i.e m = 4. 1 2 3 4 5 6 7 info x info 4 info 4 info 4 info 4 info 4 info 4 info 4 info 3 info 3 info 3 device settings result W6692 m = 4 pass 7.2.6 multiframe synchronization as specified by itu-t i.430, the q bit is transmitted from te to nt in the position normally occupied by the auxiliary framing bit (fa) in one frame out of 5, whereas the s bit is transmitted from nt to te. the s and q bit positions and multiframe structure are shown in table 7.6. the functions provided by W6692 are: - multiframe synchronization: synchronization is achived when the m bit pattern has been correctly received during 20 consecutive frames starting from frame number 1. note: criterion for multiframe synchronization is not defined in i.430 recommendation. - s bits receive and detect: when synchronization is achieved, the four received s bits in frames 1, 6, 11, 16 are stored as s1 to s4 in the sqr register respectively. a change in the recived four bits (s1-4) is indicated by an interrupt (isc in d_exir register and scc in cir register). - multiframe synchronization monitoring: multiframe synchronization is constantly monitored. the synchronization state is indicated by the msyn bit in the sqr register. - q bits transmit and f a mirroring: when multiframe synchronization is achived, the four bits q1-4 stored in the sqxr register are transmitted as the four q bits (f a -bit position) in frames 1, 6, 11 and 16. otherwise the f a bit transmitted is a mirror of the received f a -bit. at loss of synchronization, the mirroring is resumed at the next f a -bit. - the multiframe synchronization can be disabled by setting mfd bit in the d_mode register. - according to i.430 recommendation, the s/q channel can be used as operation and maintenance signalling channel. at transmitter, a s/q code for a message shall be repeated at least six times or as many as necessary to obtain the desired response. at receiver, a message shall be considered received only when the proper codes is received three consecutive times. i3_sfl
W6692 - 26 - table 7.6 multiframe structure in s/t interface frame number nt-to-te f a -bit position nt-to-te m bit nt-to-te s bit te-to-nt f a -bit position 1 2 3 4 5 one zero zero zero zero one zero zero zero zero s1 zero zero zero zero q1 zero zero zero zero 6 7 8 9 10 one zero zero zero zero zero zero zero zero zero s2 zero zero zero zero q2 zero zero zero zero 11 12 13 14 15 one zero zero zero zero zero zero zero zero zero s3 zero zero zero zero q3 zero zero zero zero 16 17 18 19 20 one zero zero zero zero zero zero zero zero zero s4 zero zero zero zero q4 zero zero zero zero 1 2 etc. one zero one zero s1 zero q1 zero 7.2.7 test functions the W6692 provides loop and test functions as follows: - digital loop via dlp bit in d_mode register: in the layer 2 block, the transmitted 2b+d data are internally looped (from hdlc transmitter to hdlc receiver), and in the pcm ports, the transmitted b channels are internally looped (from pcm inputs to pcm outputs). the clock timings are generated internally and are independent of the s bus timing. this loop function is used for test of pcm and higher layer functions, excluding layer 1. after hardware reset, W6692 will power down if s bus is not connected or if there is no signal on the s bus. in this case, the c/i command eck must be issued to power up the chip.
W6692 publication release date: october 1998 - 27 - revision a1 test functions, continued - analog loop via the c/i command eal: the analog s interface transmitter is internally connected to the s interface receiver. when the receiver has synchronized itself to the internal info 3 signal, the message "test indication" or "awake test indication" is delivered to the cir register. no signal is transmitted over the s interface. in this mode, the s interface awake detector is enabled. therefore if a level (info 2/ info 4) is detected on the s interface, this will be reported by the "awake test indication (ati)" indication. - remote loopback via rlp bit in d_mode register: the digital 2b data received from the s interface receiver is loopbacked to the s interface transmitter. the d channel is not looped. when rlp is enabled, layer 1 d channel is connected to hdlc port and dlp cannot be enabled. - transmission of special test signals via layer 1 command: * send single pulses (ssp): to send isolated single pulses of alternating polarity, with pulse width of one bit time, 250 m s apart, with a repetition frequency of 2 khz. * send continuous pulses (scp): to send continuous pulses of alternating polarity, with pulse width of bit time. the repetition frequency is 96 khz. figure 7.7 ssp and scp test signals 7.3 serial interface bus the 192 kbps s/t interface signal consists of two b channels (64 kbps each), one d channel (16 kbps) and other control signals. the multiplexing/demultiplexing functions are carried out in the serial interface bus (sib) block. in addition, the b1 and b2 channels can be individually set to carry 64 kbps or 56 kbps traffic. 250 us (a) single pulses (b) continuous pulses
W6692 - 28 - 7.4 b channel switching each b channel in s/t bus or u transceiver can be individually programmed to connect to one of the three data ports: b channel hdlc controller, pcm port 1 or pcm port 2. in addition, the pcm ports can be programmed to connect to the b channel hdlc controller for voice recording/ retrieving from main memory in answering machine applications. in this case, only extended transparent mode can be used. the switching matrix is controlled by pxc bit in pctl register and bsw1-0 bits in b1_mode and b2_mode registers as follows: a special mode is provided (bsw1-0 = 11b) in which case the pcm port can receive data from layer 1 and the hdlc receiver can receive data from pcm port simultaneously. 7.5 pcm port there are two pcm ports in W6692. each pcm port can connect to a pcm codec filter chip. these two pcm ports share the same signals except for the frame synchronization clocks. the frame synchronization clocks (pfck1-2) are 8 khz and the bit synchronization clock (pbck) is 1.536 mhz. the bit data rate is 64 kbps per port. 7.6 d channel hdlc controller there are two hdlc protocols that are used for isdn layer 2 functions: lapd and lapb. their frame formats are shown below. layer 1 /gci hdlc b1 hdlc b2 pcm1 pcm2 01 00 10 01 00 10 0 0 1 1 bsw1-0 bits pxc bit layer 1 /gci
W6692 publication release date: october 1998 - 29 - revision a1 lapb modulo 8: flag (1 octet) address (1octet) control (1octet) information (0 or n octets) fcs (2 octets) flag (1 octet) control field bits 7 6 5 4 3 2 1 0 i frame n(r) p n(s) 0 s frame n(r) p/f s s 0 1 u frame m m m p/f m m 1 1 lapb modulo 128: flag (1 octet) address (1octet) control (1 or 2 octets) information (0 or n octets) fcs (2 octets) flag (1 octet) 1st octet 2nd octet control field bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 i frame n(s) 0 n(r) p s frame x x x x s s 0 1 n(r) p/f u frame m m m p/f m m 1 1 lapd: modulo 128 only flag (1 octet) address (2 octets) control (2 octets) information (0 or n octets) fcs (2 octets) flag (1 octet) 1st octet 2nd octet control field bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 i frame n(s) 0 n(r) p/f s frame 0 0 0 0 s s 0 1 n(r) p/f u frame m m m p/f m m 1 1
W6692 - 30 - 7.6.1 d channel message transfer modes the d channel hdlc controller operates in transparent mode. chracteristics: - receive frame address recognition - address comparison maskable bit-by-bit - flag generation / deletion - zero bit insertion/ deletion - frame check sequence (fcs) generation/ check with crc_itu-t note. the lapd protocol uses the crc_itu-t for frame check sequence. the polynominal is x 16 + x 12 + x 5 + 1. for address recognition, the W6692 provides four programmable registers for individual sapi and tei values, sap1-2 and tei1-2, plus two fixed values for group sapi and tei, sapg and teig. the sapg equals feh or fch which corresponds to sapi = 63 for layer management procedure. the teig equals ffh which corresponds to tei = 127 for automatic tei assignment procedure. the address combinations are: - sap1 + tei1 - sap1 + ffh - sap2 + tei2 - sap2 + ffh - feh (fch) + tei1 - feh (fch) + tei2 - feh (fch) + ffh the receive frame address comparisons can be disabled (masked) per bit basis with the d_sam and d_tam registers, but comparisons with the sapg or teig cannot be disabled. 7.6.2 reception of frames in d channel a 128-byte fifo is provided in the receive direction. the data movement between receive fifo and micro-processor is handled by interrupts. there are two interrupt sources: receive message ready (d_rmr) and receive message end (d_rme). the d_rmr interrupt indicates that at least 64 bytes of data have been received and the message/ frame is not ended. upon d_rmr interrupt, the micro-processor reads out 64 bytes of data from the fifo. the d_rme interrupt indicates the last segment of a message or a message with length 64 bytes has been received. the length of data is less than or equal to 64 and is specified in the d_rbcl register. if the length of the last segment of message is 64, only d_rme interrupt is generated and the rbc5- 0 bits in d_rbcl register are 000000b.
W6692 publication release date: october 1998 - 31 - revision a1 the data between the opening flag and the crc field are stored in d_rfifo. for lapd frame, this includes the address field, control field and information field. when a d_rmr or d_rme interrupt is generated, the micro-processor must read out the data from d_rfifo and issues the receive message acknowledgement command (d_cmdr: rack bit) to explicitly acknowledge the interrupt. the micro-processor must handle the interrupt before more than 64 bytes of data are received. this corresponds to a maximum micro-processor reaction time of 32 ms at 16 kbps data rate. if the micro-processor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt and status bit. 7.6.3 transmission of frames in d channel a 128-byte fifo is provided in the transmit direction. if the transmit fifo is ready (which is indicated by a d_xfr interrupt ), the micro-processor can write up to 64 bytes of data into the fifo and use the xms command bit to start frame transmission. the hdlc transmitter sends the opening flag first and then sends the data in the transmit fifo. the micro-processor must write the address, control and information field of a frame into the transmit fifo. every time no more than 64 bytes of data are left in the transmit fifo, the transmitter generates a d_xfr interrupt to request another block of data. the micro-processor can then write further data to the transmit fifo and enables the subsequent transmission by issuing an xms command. if the data written to the fifo is the last segment of a frame, the micro-processor issues the xme (transmit message end) and xms command bits to finish the frame transmission. the transmitter then transmits the data in the fifo and appends crc and closing flag. if the micro-processor fails to respond the d_xfr interrupt within a given time (32 ms), a data underrun condition will occur. the W6692 will automatically reset the transmitter and send inter frame time fill pattern (all 1's) on d channel. the micro-processor is informed about this condition via an xdun (transmit data underrun) interrupt in d_exir register. the microprocessor must wait until transmit fifo ready (via xfr interrupt ), re-write data, and issue xms command to re-transmit the data. it is possible to abort a frame by issuing a d_cmdr: xrst (d channel transmitter reset) command. the xrst command resets the transmitter and causes a transmit fifo ready condition. after the micro-processor has issued the xme command, the successful termination of transmission is indicated by an d_xfr interrupt. the inter-frame time fill pattern must be all 1's, according to itu-t i.430. collisions which occur on the d channel of s interface will cause an d_exir: xcol interrupt. a xrst (transmitter reset) command must be issued and software must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data.
W6692 - 32 - 7.7 b channel hdlc controller there are two b channel hdlc controllers. each b channel hdlc controller provides two operation modes: - transparent mode characteristics: * 2 byte address field * receive address comparison maskable bit-by-bit * data between opening flag and crc (not included) stored in receive fifo * flag generation/ deletion * frame check sequence generation/ check with crc_itu-t polynominal * zero bit insertion/ deletion - extended transparent mode characteristics: * all data transmitted/ received without modification * no address comparison * no flag generation/ detection * no fcs generation/ check * no bit stuffing for pcm-hdlc connection, only extended transparent mode can be selected. the data rate in b channel can be set at 64 kbps or 56 kbps by the b1_mode (b2_mode): sw56 bit. 7.7.1 reception of frames in b channel a 128-byte fifo is provided in the receive direction. the receive fifo threshold can be set at 64 or 96 bytes by the bn_mode register. if the number of received data reaches the threshold, a receive message ready (rmr) interrupt will be generated. the operations for reception of frames differ in each mode: transparent mode : the received frame address is compared with the contents in receive address registers. in addition, the comparisons can be selectively masked bit-by-bit via address mask registers. comparison is disabled when the corresponding mask bit is "1". in addition, flag recognition, crc check and zero bit deletion are also performed. the result of crc check is indicated in bn_star:crce bit. the data between opening flag and crc field (not included) is stored in receive fifo. two interrupts are used for the reception of data. the rmr interrupt in bn_exir register indicates at least a threshold block of data have been put in the receive fifo. the rme interrupt in bn_exir register indicates the end of frame has been received. the micro-processor can read out a threshold length of data from receive fifo at rmr interrupt, or all the data in receive fifo at rme interrupt. at each rmr/ rme interrupt, micro-processor must issue a receive message acknowledgement(rack) command to explicitly acknowledge the interrupt.
W6692 publication release date: october 1998 - 33 - revision a1 the micro-processor reaction time for rmr/ rme interrupt depends on the fifo threshold setting and b channel data rate. for example, it is 8 ms if the fifo threshold is 64 and the b channel data rate is 64 kbps. if the micro-processor is late in handling the interrupt, the incoming additional bytes will result in a "data overflow" interrupt and status bit. extended transparent mode: in this mode, all data received are stored in the receive fifo without any modification. every time up to a threshold length of data has been stored in the fifo, a bn_rmr interrupt is generated. in this mode, there is no rme interrupt. the micro-processor must react to the rmr interrupt in time, otherwise a "data overflow" interrupt and status bit will be generated. 7.7.2 transmission of frames in b channel a 128-byte fifo is provided in the transmit direction. the fifo threshold can be set at 64 or 96 bytes. the transmitter and receiver use the same fifo threshold setting. the transmit operations differ in both modes: transparent mode : in this mode, the following functions are performed by the transmitter automatically: - flag generation - crc generation - zero bit insertion the fields such as address, control and information are provided by the micro-processor and are stored in transmit fifo. to start the frame transmission, the micro-processor issues a xms (transmit message start) command. the transmitter requests another block of data via xfr interrupt when more than a threshold length of vacancies are left in the fifo.the micro-processor then writes up to a threshold length of data into the fifo and activates the subsequent transmission of the frame by a xms command too. the micro-processor indicates the end of the frame transmission by issuing xme (transmit message end) and xms commands at the same time. the transmitter then transmits all the data left in the transmit fifo and appends the crc and closing flag. after this, a xfr interrupt is generated. the inter-frame time fill pattern can be programmed to 1's or flags. during the frame transmission, the micro-processor reaction time for the xfr interrupt depends on the fifo threshold setting and b channel data rate. for example, it is 8 ms if the fifo threshold is 64 and the b channel data rate is 64 kbps. if the micro-processor fails to responds within the given reaction time, the transmit fifo will be underrun. in this case, the W6692 will automatically reset the transmitter and send the inter frame time fill pattern on b channel. the micro-processor is informed about this via a transmit data underrun interrupt (xdun bit in bn_exir register). the microprocessor must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. the micro-processor can abort a frame transmission by issuing a transmitter reset command (xres bit in bn_cmdr register). the xres command resets the transmitter and sends inter frame time fill pattern on b channel. it also results in a transmit pool ready condition.
W6692 - 34 - extended transparent mode: all the data in the transmit fifo are transmitted without any modification, i.e. no flags and crcs are inserted, and no bit stuffing is performed. transmission is started by a xms command. the transmitter requests another block of data via xfr interrupt when more than a threshold length of vacancies are left in the fifo. the micro-processor reacts to this condition by writing up to a threshold length of data into the transmit fifo and issues a xms command to continue the message transmission. the micro-processor reaction time depends on the fifo threshold setting and b channel data rate. for example, it is 8 ms if the fifo threshold is 64 and the b channel data rate is 64 kbps. if the micro-processor fails to respond within the given reaction time, the transmit fifo will hold no data to transmit. in this case, the W6692 will automatically reset the transmitter and send the inter frame time fill pattern on b channel. the micro-processor is informed about this via a transmit data underrun interrupt (xdun bit in bn_exir register). the microprocessor must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. 7.8 gci mode serial interface bus the gci is a generalization and enchancement of the general purpose serial interface bus. the gci bus offers capacity for the transfer of maintenance information. in terminal applications, the gci constitute a powerful backplane bus offering sophisticated control capabilities for peripheral modules. the channel structure of the gci mode is depicted below: channel structure of the W6692 gci mode: b1 b2 mon d c i null null b1 b2 monitor d c/i mr mx 1 st octet 2 nd octet 3 rd octet 4 th octet figure 7.8 gci mode channel structure the first two octets constitute the two 64 kbps b channels. the third octet is the monitor channel. it is used for the exchange of data between the W6692 and the other attached device using the gci monitor channel protocol. the fourth octet (control channel) contains: two bits for the 16 kbps d channel, a 4-bit c/i channel (command/indication channel), and 2-bit mr and mx for supporting the monitor channel handshaking protocol.
W6692 publication release date: october 1998 - 35 - revision a1 the W6692 gci mode signals are: din/dout : 768 kbps dcl : 1.536 mhz input fsc : 8 khz input 7.8.1 gci mode c/i channel handling the command/indication channel carries real-time status information between the W6692 and another device connected to the gci bus interface. one c/i channel conveys the commands and indications between a layer 1 device and layer 2 device. this c/i channel is access via register cir (in receive direction, layer 1 to layer 2) and register cix (in transmit direction, layer 2 to layer 1). the c/i code is 4-bit long. in the receive direction, the code from layer 1 is continuously monitored, with an interrupt being generated anytime a change occurs. a new code must be found in two consecutive gci frames to be consided valid and to trigger a c/i code change interrupt status (double last look criterion). in the transmit direction, the code written in cix is continuously transmitted in the channel. 7.8.2 gci mode monitor channel handling the monitor channel protocol is a handshake protocol used for high speed information exchange between the W6692 and other devices. in the W6692 gci mode only one monitor channel is available. the monitor channel is necessary for: programming and controlling devices attached to the gci interface. data exchange between two microprocessor systems attached to two different devices on one gci backplane. use of the monitor channel avoids the necessity of a dedicated serial communication path between two systems. the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the monitor channel receiver (mor) and monitor channel transmit (mox) bits. when data is placed into the monitor channel and the mx bit is activated. this data will be transmitted repeatedly once per 8 khz frame until the transfer is acknowledged via the mr bit. the microprocessor may either enforce a 1 (idle state) in mr, mx by setting the control bit mrc or mxc (mocr register) to 0, or enable the control of these bits internally by the W6692 according to the monitor channel protocol. thus, before a data exchange can begin, the control bit mrc, or mxc should be set to 1 by the microprocessor. the relevant status bits are: for the reception of monitor data: mdr (monitor channel data received) ? mer (monitor channel end of reception) for the transmission of monitor data: mda (monitor channel data acknowledged) ? mab (monitor channel data abort) about the status bit mac (monitor channel transmit active) indicates whether a transmission is progress .
W6692 - 36 - if set mac = 0, the previous transmission has been terminated. before starting a transmission, the microprocessor should verify that the transmitter is inactive. if set mac = 1, after having written data into the monitor transmit channel (mox) register, the microprocessor sets this bit to 1. this enables the mx bit to go active (0), indicating the presence of valid monitor data (contents of mox) in the corresponding frame. the receiing device stores the monitor byte in its mor (monitor receive register) and generates a mdr (monitor channel data receive) interrupt status. alerted by the mdr interrupt, the microprocessor reads the mor register. when it is ready to accept data, it sets the mr control bit mrc to 1 to enable the receiver to store succeeding monitor channel bytes and acknowledge them according to the monitor channel protocol. in addition, it enables other monitor channel interrupts by setting monitor channel interrupt enable to 1. the first monitor channel byte is acknowledged by the receiving device setting the mr bit to 0. this causes a mda (monitor channel data acknowledge) interrupt status at the transmitter. a new monitor channel data byte can now be written by the microprocessor in mox register. the mx bit is still in the active (0) state. the transmitter indicates a new byte in the monitor channel by returning the mx bit active after sending it once in the inactive state. the receiver stores the monitor channel byte in mor register and generates a new mdr interrupt status. when the microprocessor has read the mor register , the receiver acknowledges the data by returning the mr bit active after sending it once in the inactive state. this in turn causes the transmitter to generate a mda interrupt status. this 2 mda interrupt t write data t mdr interrupt t read data t mda interrupt 2 handshake procedure is repeated as long as the transmitter has data to send. when the last byte has been acknowledged by the receiver (mda interrupt status), the microprocessor sets the monitor channel transmit control bit mxc to 0. this enforces an inactive (1) state in the mx bit. two frames of mx inactive signifies the end of a message. thus, a mer (monitor channel end of reception) interrupt status is generated by the receiver when the mx is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the mr control bit mrc to 0, which in turn enforces an inactive state in the mr bit. this marks the end of the transmittion, making the mac (monitor channel active) bit return to 0. during a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive mr bit value in two consecutive frames. this is effected by the microprocessor writing the mr control bit mrc to 0. an aborted transmission is indicated by a mab (monitor channel data abort) interrupt status at the transmitter. 7.9 pci interface circuit 7.9.1 pci slave mode and configuration serial eeprom W6692 implements slave (target) mode function which meets pci local bus specification revision 2.1. all the signals are 5v, 33 mhz compatible. a signle function, type 00h configuration header is implemented for control of the internal isdn device and external peripheral device(s). memory mode and/or io mode can be used for W6692's register access. after power on reset, W6692 starts to read configuration data from serial eeprom port. the first word read is vendor id, if it equals ffffh, default configuration data is used, otherwise, the configuration data stored in serial eeprom is used. the default configuration data is as follows:
W6692 publication release date: october 1998 - 37 - revision a1 vendor id : 1050h (winbond's id) device id : 6692h class code : 02 80 00h revision id : 00h subsystem vendor id : ffffh subsystem id : ffffh memory base address register : enabled and implemented at 10h io base address register : enabled and implemented at 14h a 9346/93c46 type serial eeprom is used for configuration data storage. the format is as follows: address 15 8 7 0 0 15 vendor id 0 1 15 device id 0 2 7 interface code 0 7 revision id 0 3 7 base class code 0 7 subclass code 0 4 15 subsystem vendor id 0 5 15 subsystem id 0 6 15 address register control 0 address register control: 15 14 13 12 0 men ien pre not used figure 7.9 serial eeprom data format important note: in all pc platforms, burst mode is used very often for memory access. because W6692 does not support burst mode, it is recommended not to use memory access for W6692's internal registers and data.
W6692 - 38 - the address register control determines the address registers implementation. bit 13 is the prefetchable bit in memory base address register. men ien location 10h location 14h pre used 1 1 memory base address reg. io base address reg. yes 1 0 memory base address reg. not implemented yes 0 1 io base address reg. not implemented no 0 0 not implemented not implemented no eeprom empty memory base address reg. io base address reg. pre = 1 in all cases, memory base address register allocates 4096 byte spaces and io base address register allocates 256 byte space. W6692 provides one register for on-board programming of the serial eeprom. this register called epctl register is at offset address fch. the format is: 7 3 2 1 0 reserved en sk cs sdo the data written at bits 2-0 are directly output on pins epsk, epcs and epsdo if en = 1. the outputs are disabled if en = 0. en bit does not affect the power on configuration read. for example, to generate the following waveform, the write data sequence is: sequence en sk cs sdo 1 1 0 0 0 2 1 1 1 1 3 1 0 1 1 4 1 1 1 0 5 1 0 1 0 epcs epsk epsdo
W6692 publication release date: october 1998 - 39 - revision a1 7.9.2 cascade structure of interrupt sources the W6692 uses cascade structure to record the causes of various interrupts. the interrupt structure is shown in figure 7.10. a read of the ista register clears all the interrupts except d_exi, b1_exi and b2_exi bits. these three bits are cleared if their corresponding extended interrupt registers are cleard. b1_exi bit is cleared by reading the b1_exir register and b2_exi bit is cleared by reading the b2_exir register. reading of b1_exir or b2_exir register clears all the bits in it. the b1_exim and b2_exim registers mask the corresponding bits in the b1_exir and b2_exir registers. to clear the d_exi bit, all the bits in d_exir must first be cleared. a read of the d_exir register clears all the bits except the isc bit. the isc bit is cleared by a read of cir and sqr registers. an isc interrupt may originate from - a change in the received indication code (icc bit in cir register) or - a change in the received s code (scc bit in cir register). the icc interrupt can not be disabled while the scc interrupt can be disbled by clearing the scie bit in sqx register. bits scc and icc are cleared by a read of sqr and cir. d_exim register masks the corresponding bits in d_exir register. if the d_exim: isc bit is set to one, it masks the icc and scc interrupts. the icc or scc bit is set whenever a new code is loaded in cir or sqr. but if the previous register content has not been read out in case of a code change, the new code will not be loaded. the code registers are buffered with a fifo size of two. thus if several consecutive code changes are detected, only the first and the last code is obtained at the first and second register read, respectively.
W6692 - 40 - figure 7.10 W6692 interrupt structure d_exim isc moc tin2 xcol xdun rdov wexp texp d_exir isc moc tin2 xcol xdun rdov wexp texp sqx q2 q1 scie q4 q3 sqr s2 s1 scie msyn xind0 xind1 s4 s3 cir codr2 codr3 icc scc codr0 codr1 irq pin imask d_exi xint0 xint1 d_xfr d_rme d_rm b2_exi b1_exi ista d_exi xint0 xint1 d_xfr d_rme d_rmr b2_exi b1_exi b1_exim rdov rme rmr xdun xfr b1_exir rdov rme rmr xdun xfr b2_exim rdov rme rmr xdun xfr b2_exir rdov rme rmr xdun xfr
W6692 publication release date: october 1998 - 41 - revision a1 7.10 peripheral control in pci card with pots application, the peripheral devices such as codec, dtmf and slic can be directly controlled by W6692, therefore preclude the need for another pci controller chip. the peripheral control function includes timer, interrupt inputs and programmable ios or microprocessor interface. there are two timers implemented in W6692: d_timr and timr2. d_timr is a long period timer whcich can be used to control the 1 sec, 2 sec on/off of ring tone. while timr2 is a short period timer which can be used to generate the tens hertz of ring signal. address interrupt status interrupt mask output pin period cyclic d_timr 10h dexir: texp dexim: texp no (0..6) x 2.048 s +(1..32) x 64 ms yes (cnt = 7) timr2 4ch dexir: tin2 dexim: tin2 tout2 (1..63) ms yes (tmd = 1) tout2 toggles when timr2 counts down to zero. for example, if the timer period is 1 ms, then the period of tout2 is 2 ms. there are two interrupt input pins: xintin0, xintin1. whenever signal level changes (eith rising or falling), a maskable interrupt is generated which in turn will make an interrupt request on pci bus if it is unmasked. the interrupt status bits are ista: xint0, ista: xint1. the mask bits are imask: xint0, imask: xint1. in addition, the signal level can be read at bits sqr: xind0, sqr; xind1. these pins can be used for monitor of slic hook state and/or dtmf data valid status. the io interface can be programmed as simple io (pctl: xmode = 0) or 8-bit microprocessor interface (pctl: xmode = 1). as simple ios, the directions of the 11 pins are selected via oe5-0 bits in pctl register and the read/write data accessed via xaddr and xdata registers. as output, the register data is output on the pin, as input, the current level of pin is read in. in this mode, a maximum of 11 io ports are supported. if programmed as 8-bit microprocessor mode, an 8-bit multiplexed bus is used to control peripheral deveces. the address and data are multiplexed on xad7-0. xale is used for address latch and xrdb, xwrb are used for read/write strobe. to access peripheral device, first write the desired address in xaddr register and then read/write data at xdata register. in this mode, a maximum of 256 byte ports can be supported by adding some glue ttls on board.
W6692 - 42 - 8. register descriptions 8.1 chip control and d_ch hdlc controller table 8.1 register address map: chip control and d channel hdlc section offset access register name description 8.1.1 00 r d_rfifo d channel receive fifo 8.1.2 04 w d_xfifo d channel transmit fifo 8.1.3 08 w d_cmdr d channel command register 8.1.4 0c r/w d_mode d channel mode control 8.1.5 10 r/w d_timr d channel timer control 8.1.6 14 r_clear ista interrupt status register 8.1.7 18 r/w imask interrupt mask register 8.1.8 1c r_clear d_exir d channel extended interrupt 8.1.9 20 r/w d_exim d channel extended interrupt mask 8.1.10 24 r d_star d channel status register 8.1.11 28 r d_rsta d channel receive status 8.1.12 2c r/w d_sam d channel address mask 1 8.1.13 30 r/w d_sap1 d channel individual sapi 1 8.1.14 34 r/w d_sap2 d channel individual sapi 2 8.1.15 38 r/w d_tam d channel address mask 2 8.1.16 3c r/w d_tei1 d channel individual tei 1 8.1.17 40 r/w d_tei2 d channel individual tei 2 8.1.18 44 r d_rbch d channel receive frame byte count high 8.1.19 48 r d_rbcl d channel receive frame byte count low 8.1.20 4c w timr2 timer 2 8.1.21 50 r/w l1_rc gci layer 1 ready code 8.1.22 54 r/w d_ctl d channel control register 8.1.23 58 r cir command/indication receive 8.1.24 5c w cix command/indication transmit 8.1.25 60 r sqr s/q channel receive register 8.1.26 64 w sqx s/q channel transmit register 8.1.27 68 r/w pctl peripheral control register 8.1.28 6c r mor monitor receive channel 8.1.29 70 r/w mox monitor transmit channel 8.1.30 74 r mosr monitor channel status register 8.1.31 78 r/w mocr monitor channel control register 8.1.32 7c r/w gcr gci mode control register 8.1.33 f4 r/w xaddr peripheral address register 8.1.34 f8 r/w xdata peripheral data register 8.1.35 fc w epctl serial eeprom control
W6692 publication release date: october 1998 - 43 - revision a1 table 8.2 register summary: chip control and d channel hdlc offset r/w name 7 6 5 4 3 2 1 0 00 r d_rfifo 04 w d_xfifo 08 w d_cmdr rack rrst stt xms xme xrst 0c r/w d_mode mms ract tms tee mfd dlp rlp 10 r/w d_timr cnt2 cnt1 cnt0 val4 val3 val2 val1 val0 14 r_clr ista d_rmr d_rme d_xfr xint1 xint0 d_exi b1_exi b2_exi 18 r/w imask d_rmr d_rme d_xfr xint1 xint0 d_exi b1_exi b2_exi 1c r_clr d_exir rdov xdun xcol tin2 moc isc texp wexp 20 r/w d_exim rdov xdun xcol tin2 moc isc texp wexp 24 r d_star xdow xbz drdy 28 r d_rsta rdov crce rmb 2c r/w d_sam sam7 sam6 sam5 sam4 sam3 sam2 sam1 sam0 30 r/w d_sap1 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 34 r/w d_sap2 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 38 r/w d_tam tam7 tam6 tam5 tam4 tam3 tam2 tam1 tam0 3c r/w d_tei1 ta17 ta16 ta15 ta14 ta13 ta12 ta11 ta10 40 r/w d_tei2 ta27 ta26 ta25 ta24 ta23 ta22 ta21 ta20 44 r d_rbch vn1 vn0 lov rbc12 rbc11 rbc10 rbc9 rbc8 48 r d_rbcl rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 4c w timr2 tmd 0 tcn5 tcn4 tcn3 tcn2 tcn1 tcn0 50 r/w l1_rc rc3 rc2 rc1 rc0 54 r/w d_ctl wtt1 wtt2 srst tps ops1 ops0 58 r cir scc icc codr3 codr2 codr1 codr0 5c w cix codx3 codx2 codx1 codx0 60 r sqr xind1 xind0 msyn scie s1 s2 s3 s4 64 w sqx scie q1 q2 q3 q4 68 r/w pctl oe5 oe4 oe3 oe2 oe1 oe0 xmode pxc 6c r mor 70 r/w mox 74 r_clr mosr mdr mer mda mab 78 r/w mocr mrie mrc mxie mxc 7c r/w gcr mac tlp grlp spu pd ge f4 r/w xaddr xa7/io7 xa6/io6 xa5/io5 xa4/io4 xa3/io3 xa2/io2 xa1/io1 xa0/io0 f8 r/w xdata xd7 xd6 xd5 xd4 xd3 xd2/io10 xd1/io9 xd0/io8 fc w epctl en sk cs sdo
W6692 - 44 - 8.1.1 d_ch receive fifo d_rfifo read address 00h the d_rfifo has a length of 128 bytes. after a d_rmr interrupt, exactly 64 bytes are available. after a d_rme interrupt, the number of bytes available equals rbc5-0 bits in the d_rbcl register. 8.1.2 d_ch transmit fifo d_xfifo write address 04h the d_xfifo has a length of 128 bytes. after an d_xfr interrupt, up to 64 bytes of data can be written into this fifo for transmission. at the first time, up to 128 bytes of data can be written. 8.1.3 d_ch command register d_cmdr write address 08h value after reset: 00h 7 6 5 4 3 2 1 0 rack rrst stt xms xme xrst rack receive acknowledge after a d_rmr or d_rme interrupt, the processor must read out the data in d_rfifo and then sets this bit to acknowledge the interrupt. rrst receiver reset setting this bit resets the d_ch hdlc receiver and clears the d_rfifo data. stt start timer the d_ch hardware timer is started when this bit is set to one. the timer is stopped when it expires or by a write of the d_timr register. note that the timer must be in external mode. xms transmit message start/continue setting this bit will start or continue the transmission of a frame. the opening flag is automatically added by the hdlc controller. xme transmit message end setting this bit indicates the end of frame transmission. the d_ch hdlc controller automatically appends the crc and the closing flag after the data transmission. note: if the frame 64 bytes, xme plus xms commands must be issued at the same time. xrst transmitter reset setting this bit resets the d_ch hdlc transmitter and clears the d_xfifo. the transmitter will send inter frame time fill pattern (which is 1's) immediately. this command also results in a transmit fifo ready condition.
W6692 publication release date: october 1998 - 45 - revision a1 8.1.4 d_ch mode register d_mode read/write address 0ch value after reset: 00h 7 6 5 4 3 2 1 0 mms ract tms tee mfd dlp rlp mms message mode setting determines the message transfer mode of the d_ch hdlc controller: mms mode address bytes first byte address comparison with: second byte address comparison with: 0 transparent mode 2 d_sap1, d_sap2, sapg d_tei1, d_tei2, teig notes: 1. d_sap1, d_sap2: two programmable address values for the first received address byte; sapg = fixed value fc/feh. d_tei1, d_tei2 : two programmable address values for the second received address byte; teig = fixed value ffh. 2: the first byte address comparison can be masked by d_sam register, and the second byte address comparison can be masked by d_tam register. but the comparisons with sapg and teig cannot be disabled. ract receiver active setting this bit activates the d_ch hdlc receiver. this bit can be read. the receiver must be in active state in order to receive data. tms timer mode setting sets the operating mode of the d_ch timer. in the external mode (tms = 0), the timer is controlled by the processor. it is started by setting the stt bit in d_cmdr and is stopped by a write of the d_timr register or when it expires. when the timer expires, a maskable d_exp interrupt is generated. in the internal mode (tms = 1), the timer is used for internal test purposes. it should not be selected for normal chip operation. tee terminal equipment function enable the terminal equipment function is enabled when this bit is "1". the supported functions are: - watchdog timer, enabled when tee = 1 and d_ctl: tps =1 - exchange awake, enabled when tee = 1 and d_ctl: tps =0 when the watchdog timer has been enabled, the micro-processor has to program the wtt1, 2 bits in a specified manner within 1024 ms to reset and restart the timer. otherwise, the timer will expire in 1024 ms and a wexp interrupt together with a 125 m s reset pulse on trst pin is generated. the exchange awake condition is initiated by c/i code change condition. a 16 ms reset pulse on trst pin is generated. switching tps bit will reset the watchdog timer. the tee bit is cleared only by a hardware reset.
W6692 - 46 - mfd multiframe disable this bit is used to enable or disable the multiframe structure on s/t interface: 0 : multiframe is enabled 1 : multiframe is disabled dlp digital loopback setting this bit activates the digital loopback function. the transmitted digital 2b+d channels are looped to the received 2b+d channels. note that after hardware reset, the internal clocks will turn off if the s bus is not connected or if there is no signal on the s bus. in this case, the c/i command eck must be issued to enable loopback function. rlp remote loopback setting this bit to "1" activates the remote loopback function. the received 2b channels from the s interface are looped to the transmitted 2b channels of s interface. the d channel is not looped in this loopback function. 8.1.5 d_ch timer register d_timr read/write address 10h value after reset: ffh 7 6 5 4 3 2 1 0 cnt2 cnt1 cnt0 val4 val3 val2 val1 val0 cnt together with val determine the time period t2 after which a texp interrupt will be generated: t2 = cnt * 2.048 s + t1 with t1 = (val +1) * 0.064 s the timer is started by setting the stt bit in d_cmdr and will be stopped when a texp interrupt is generated or the d_timr register is written. note: if cnt is set to 7, a texp interrupt is generated periodically at every expiration of t1. this register can be read only after the timer has been started. the read value indicates the timer's current count value. in case layer 1 is not activated, a c/i command "eck" must be issued in addition to the stt command to start the timer. 8.1.6 interrupt status register ista read_clear address 14h value after reset: 00h 7 6 5 4 3 2 1 0 d_rmr d_rme d_xfr d_exi b1_exi b2_exi d_rmr d_ch receive message ready a 64-byte data is available in the d_rfifo. the frame is not complete yet.
W6692 publication release date: october 1998 - 47 - revision a1 d_rme d_ch receive message end the last part of a frame with length > 64 bytes or a whole frame with length 64 bytes has been received. the whole frame length is obtained from d_rbch + d_rbcl registers. the length of data in the d_rfifo equals: data length = rbc5-0 if rbc5-0 1 0 data length = 64 if rbc5-0 =0 d_xfr d_ch transmit fifo ready this bit indicates that the transmit fifo is ready to accept data. up to 64 bytes of data can be written into the d_xfifo. an d_xfr interrupt is generated in the following cases: - after an xms command, when 3 64 bytes of xfifo is empty - after an xms together with an xme command is issued, when the whole frame has been transmitted - after hardware reset xint1 xintin1 interrupt this bit indicates that level change occurs at xintin1 pin. both positive and negative edges will cause an interrupt. xint0 xintin1 interrupt this bit indicates that level change occurs at xintin0 pin. both positive and negative edges will cause an interrupt. d_exi d_ch extended interrupt this bit indicates that at least one interrupt bit has been set in d_exir register. b1_exi b1_ch extended interrupt this bit indicates that at least one interrupt bit has been set in b1_exir register. b2_exi b2_ch extended interrupt this bit indicates that at least one interrupt bit has been set in b2_exir register. note: a read of the ista register clears all bits except d_exi, b1_exi and b2_exi bits. d_exi bit is cleared when all bits in d_exir register are cleared, b1_exi bit is cleared by reading b1_exi register and b2_exi bit is cleared by reading b2_exir register.
W6692 - 48 - 8.1.7 interrupt mask register imask r/w address 18h value after reset: ffh 7 6 5 4 3 2 1 0 d_rmr d_rme d_xfr xint1 xint0 d_exi b1_exi b2_exi setting the bit to "1" masks the corresponding interrupt source in ista register. masked interrupt status bits are read as zero. they are internally stored and pending until the mask bits are zero. setting the d_exi, b1_exi or b2_exi bit to "1" masks all the interrupts in d_exir, b1_exir or b2_exir register, respectively. 8.1.8 d_ch extended interrupt register d_exir read_clear address 1ch value after reset: 00h 7 6 5 4 3 2 1 0 rdov xdun xcol moc isc texp wexp rdov receive data overflow frame overflow (too many short frames) or data overflow occurs in the receive fifo. in data overflow, the incoming data will overwrite the data in the receive fifo. if rdov interrupt occurs, software has to reset the receiver and discard the data received. xdun transmit data underrun this interrupt indicates the d_xfifo has run out of data. in this case, the W6692 will automatically reset the transmitter and send the inter frame time fill pattern (all 1's) on d channel. the microprocessor must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. xcol transmit collision this bit indicates a collision on the s-bus has been detected. a xrst command must be issued and software must wait until transmit fifo ready (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. tin2 timer 2 expiration this bit is set when timer 2 counts down to zero. moc monitor channel status change a change in the gci mode monitor channel status register (mosr) has occurred. a new monitor channel byte is stored in the mor register. isc indication or s channel change a change in the layer 1 indication code or multiframe s channel has been detected. the actual value can be read from cir or sqr registers.
W6692 publication release date: october 1998 - 49 - revision a1 texp d_ch timer expiration expiration occurs in the d_ch timer. the timer must be in external mode. wexp watchdog timer expiration expiration occurs in the watch dog timer. a reset pulse with 125 m s pulse width is also generated on the trst pin. see d_ctl register for watch dog timer control. 8.1.9 d_ch extended interrupt mask register d_exim read/write address 20h value after reset: ffh 7 6 5 4 3 2 1 0 rdov xdun xcol tin2 moc isc texp wexp setting the bit to "1" masks the corresponding interrupt source in d_exir register. masked interrupt status bits are read as zero. they are internally stored and pending until the mask bits are zero. all the interrupts in d_exir will be masked if the imask: d_exi bit is set to "1". 8.1.10 d_ch status register d_star re ad address 24h value after reset: 0xh 7 6 5 4 3 2 1 0 xdow xbz drdy xdow transmit data overwritten at least one byte of data has been overwritten in the d_xfifo. this bit is set by data overwritten condition and is cleared only by xrst command. xbz transmitter busy this bit indicates the d_hdlc transmitter is busy. the xbz bit is active from the transmission of opening flag to the transmission of closing flag. drdy d channel ready this bit indicates the status of layer 1 d channel. 0: the layer 1 d channel is not ready. no transmission is allowed. 1: the layer 1 d channel is ready. layer 2 can transmit data to layer 1.
W6692 - 50 - 8.1.11 d_ch receive status register d_rsta read address 28h value after reset: 20h 7 6 5 4 3 2 1 0 rdov crce rmb rdov receive data overflow a "1" indicates that the d_rfifo is overflow. the incoming data will overwrite data in the receive fifo. the data overflow condition will set both the status and interrupt bits. it is recommended that software must read the rdov bit after reading data from d_rfifo at rmr or rme interrupt. the software must abort the data and issue a rrst command to reset the receiver if rdov = 1. the frame overflow condition will not set this bit. crce crc error this bit indicates the result of frame crc check: 0: crc correct 1: crc error rmb receive message aborted a "1" means that a sequence of seven 1's was received and the frame is aborted. software must issue rrst command to reset the receiver. note: normally d_rsta register should be read by the micro-processor after a d_rme interrupt. the contents of d_rsta are valid only after a d_rme interrupt and remain valid until the frame is acknowledged via a rack bit. 8.1.12 d_ch sapi address mask d_sam read/write address 2ch value after reset: 00h 7 6 5 4 3 2 1 0 sam7 sam6 sam5 sam4 sam3 sam2 sam1 sam0 this register masks(disables) the first byte address comparison of the incoming frame. if the mask bit is "1" the corresponding bit comparisons with d_sap1, d_sap2 are disabled. comparison with sapg is always performed. note: for the lapd frame, the least significant two bits are the c/r bit and ea = 0 bit. it is suggested that the comparison with c/r bit be masked. ea = 0 for two octet address frame e.g lapd, ea = 1 for one octet address frame. 8.1.13 d_ch sapi1 register d_sap1 read/write address 30h value after reset: 00h 7 6 5 4 3 2 1 0 sa17 sa16 sa15 sa14 sa13 sa12 sa11 sa10 this register contains the first choice of the first byte address of received frame. for lapd frame, sa17 - sa12 is the sapi value, sa11 is c/r bit and sa10 is zero.
W6692 publication release date: october 1998 - 51 - revision a1 8.1.14 d_ch sapi2 register d_sap2 read/write address 34h value after reset: 00h 7 6 5 4 3 2 1 0 sa27 sa26 sa25 sa24 sa23 sa22 sa21 sa20 this register contains the second choice of the first byte address of received frame. for lapd frame, sa27 - sa22 is the sapi value, sa21 is c/r bit and sa20 is zero. 8.1.15 d_ch tei address mask d_tam read/write address 38h value after reset: 00h 7 6 5 4 3 2 1 0 tam7 tam6 tam5 tam4 tam3 tam2 tam1 tam0 this register masks(disables) the second byte address comparison of the incoming frame. if the mask bit is "1" the corresponding bit comparisons with d_tei1, d_tei2 are disabled. comparison with teig is always performed. note: for the lapd frame, the least significant bit is the ea = 1 bit. 8.1.16 d_ch tei1 register d_tei1 read/write address 3ch value after reset: 00h 7 6 5 4 3 2 1 0 ta17 ta16 ta15 ta14 ta13 ta12 ta11 ta10 ta17 - ta10 this register contains the first choice of the second byte address of received frame. for lapd frame, ta17 - ta11 is the tei value, ta10 is ea = 1. 8.1.17 d_ch tei2 register d_tei2 read/write address 40h value after reset: 00h 7 6 5 4 3 2 1 0 ta27 ta26 ta25 ta24 ta23 ta22 ta21 ta20
W6692 - 52 - ta27 - ta20 this register contains the second choice of the second byte address of received frame. for lapd frame, ta27 - ta21 is the tei value, ta20 is ea = 1. 8.1.18 d_ch receive frame byte count high d_rbch read address 44h value after reset: 00h 7 6 5 4 3 2 1 0 vn1 vn0 lov rbc12 rbc11 rbc10 rbc9 rbc8 vn1-0 chip version number this is the chip version number. it is read as 00b. lov length overflow a "1" in this bit indicates 3 4097 bytes are received and the frame is not yet complete. this bit is valid only after an d_rme interrupt and remains valid until the frame is acknowledge via the rack command. rbc12-8 receive byte count four most significant bits of the total frame length. these bits are valid only after an d_rme interrupt and remain valid until the frame is acknowledge via the rack command. 8.1.19 d_ch receive frame byte count low d_rbcl read address 48h value after reset: 00h 7 6 5 4 3 2 1 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 rbc7-0 receive byte count eight least significant bits of the total frame length. bits rbc5-0 also indicate the length of the data currently available in d_rfifo. these bits are valid only after an d_rme interrupt and remain valid until the frame is acknowledged via the rack command. 8.1.20 timer 2 timr2 write addres s 4ch value after reset: 00h 7 6 5 4 3 2 1 0 tmd 0 tcn5 tcn4 tcn3 tcn2 tcn1 tcn0
W6692 publication release date: october 1998 - 53 - revision a1 tmd timer 2 mode 0: one shot count down mode. the timer starts when it is written a non-zero count value and stops when it reaches zero. 1: cyclic timer mode. the timer starts when it is written a non-zero count value and counts cyclically (periodically) with the count value. in both cases, a maskable interrupt tin2 is generated and tout2 pin toggles every time the timer reaches zero. when timer starts, tout2 changes to low and toggles at timer expiration. therefore, the period of tout2 is twice of count value. in both cases, timer counts with the new value if it is written again before expiration. tcn5-0 timer 2 count value 0: timer is off. 1-31: timer count value in unit of ms. 8.1.21 layer 1_ready code l1_rc read/write address 50h value after reset: 0ch 7 6 5 4 3 2 1 0 rc3 rc2 rc1 rc0 rc3-0 ready code when gci bus is being enabled, these four programmable bits are allowed to program different layer 1_ready code (ai: activation indication) by user. for example: siemens peb2091: ai = 1100, motorola mc145572: ai = 1100. 8.1.22 d_ch control register d_ctl read/write address 54h value after reset: 00h 7 6 5 4 3 2 1 0 wtt1 wtt2 srst tps ops1 ops0 wtt1, 2 watchdog timer trigger 1, 2 when the watchdog timer has enabled (d_mode: tee = 1 and d_ctl: tps = 1), the micro- processor has to program the wtt1, 2 bits in the following sequences within 1024 ms to reset and restart the timer. otherwise, the timer will expire after 1024 ms and a wexp interrupt together with a 125 m s reset pulse on trst pin are generated: sequence wtt1 wtt2 1 1 0 2 0 1 switching tps bit from 0 to 1 or from 1 to 0 resets the watchdog timer.
W6692 - 54 - srst software reset when this bit is set to "1", a software reset signal is activated. the effects of this reset signal are equivalent to the hardware reset pin , except that it does not reset the pci interface circuit. this bit is not auto-clear, the software must write "0" to this bit to exit from the reset mode. note: when srst = 1, the chip is in reset state. read or write to any of the registers is inhibited at this time. the srst bit is write only. tps trst reset pulse select this bit selects the source of reset pulse on trst pin. it is valid only when the terminal equipment functions are enabled. 0: exchange awake a 16 ms reset pulse is generated when the a layer 1 indication code change has been detected. 1: watchdog timer a 125 m s reset pulse is generated as a result of the watchdog timer expiration. switching tps bit from 0 to 1 or from 1 to 0 resets the watchdog timer. ops1-0 output phase delay compensation select1-0 these two bits select the output phase delay compensation. ops1 ops0 effect 0 0 no output phase delay compensation 0 1 output phase delay compensation 260 ns 1 0 output phase delay compensation 520 ns 1 1 output phase delay compensation 1040 ns 8.1.23 command/indication receive register cir read address 58h value after reset: 0fh 7 6 5 4 3 2 1 0 scc icc codr3 codr2 codr1 codr0 scc s channel change a change in the received 4-bit s channel has been detected. the new code can be read from the sqr register. this bit is cleared by a read of the sqr register. icc indication code change a change in the received indication code has been detected. the new code can be read from the cir register. this bit is cleared by a read of the cir register.
W6692 publication release date: october 1998 - 55 - revision a1 codr3-0 layer 1 indication code value of the received layer 1 indication code. note: if s/t layer 1 function is disabled and gci bus is enabled (ge bit = 1 in gcr register), cir register is used to receive layer 1 indication code from u transceiver. in this case, scc bit is not used and the supported indication codes are: indication symbol code descriptions deactivation confirmation dc 1111 idle code on gci interface power up indication pu 0111 u transceiver power up 8.1.24 command/indication transmit register cix write address 5ch value after reset: 0fh 7 6 5 4 3 2 1 0 codx3 codx2 codx1 codx0 codx3-0 layer 1 command code value of the command code transmitted from layer 2 to layer 1. note: if s/t layer 1 function is disabled and gci bus is enabled (ge bit = 1 in gcr register), cix register is used to issue layer 1 command code to u transceiver. in this case, the supported command code is: command symbol code descriptions activate request command ar 1000 activate request command 8.1.25 s/q channel receive register sqr read address 60h value after reset: xfh 7 6 5 4 3 2 1 0 xind1 xind0 msyn scie s1 s2 s3 s4 xind1 xintin1 data this bit reflects the current level of xintin1 pin. xind0 xintin0 data this bit reflects the current level of xintin0 pin. msyn multiframe synchronization when this bit is "1", a multiframe synchronization is achived, i.e the the s/t receiver has synchronized to the received f a and m bit patterns. scie s channel change interrupt enable this bit reflects the bit written in the sqx register.
W6692 - 56 - s1-4 received s bits these are the s bits received in nt to te direction in frames 1, 6, 11 and 16. s1 is in frame 1, s2 is in frame 6 etc. 8.1.26 s/q channel transmit register sqx write address 64h value after reset: 0fh 7 6 5 4 3 2 1 0 scie q1 q2 q3 q4 scie s channel change interrupt enable this bit is used to enable/disable the generation of cir:scc status bit and interrupt. 0: status bit and interrupt are disabled. 1: status bit and interrupt are enabled. q1-4 transmitted q bits these are the transmitted q channels in f a bit positions in frames 1, 6, 11 and 16. q1 is in frame 1, q2 is in frame 6 etc. 8.1.27 peripheral control register pctl read/write address 68h value after reset: 00h 7 6 5 4 3 2 1 0 oe5 oe4 oe3 oe2 oe1 oe0 xmode pxc oe5 direction control for io10 used when xmode = 0 only. 0: pin io10 is input. 1: pin io10 is output. oe4 direction control for io9-8 used when xmode = 0 only. 0: pin io9-8 are inputs. 1: pin io9-8 are outputs. oe3 direction control for io7-6 used when xmode = 0 only. 0: pin io7-6 are inputs. 1: pin io7-6 are outputs.
W6692 publication release date: october 1998 - 57 - revision a1 oe2 direction control for io5-4 used when xmode = 0 only. 0: pin io5-4 are inputs. 1: pin io5-4 are outputs. oe1 direction control for io3-2 used when xmode = 0 only. 0: pin io3-2 are inputs. 1: pin io3-2 are outputs. oe0 direction control for io1-0 used when xmode = 0 only. 0: pin io1-0 are inputs. 1: pin io1-0 are outputs. xmode peripheral bus mode 0: simple programmable io. this is the default state. xaddr register and xdata register are used for data access. 1: 8-bit multiplexed microprocessor bus. pins io7-0 are used as xad7-0, io8 as xale, io9 as xrdb and io10 as xwrb. xaddr register is used for peripheral address generation and xdata register is used for peripheral data access. pxc pcm cross-connect this bit determines whether or not the pcm ports are cross-connected with the b channel ports. the setting of pxc is independent of the bsw1-0 bits. pxc connection 0 pcm1 ? b1, pcm2 ? b2 1 pcm1 ? b2, pcm2 ? b1 8.1.28 monitor receive channel mor read address 6ch value after reset: ffh 7 6 5 4 3 2 1 0 contains the monitor channel data received in gci monitor channel according to the monitor channel protocol.
W6692 - 58 - 8.1.29 monitor transmit channel mox read/write address 70h value after reset: ffh 7 6 5 4 3 2 1 0 contains the monitor channel data transmitted in gci monitor channel according to the monitor channel protocol. 8.1.30 monitor channel status register mosr read_clear address 74h value after reset: 00h 7 6 5 4 3 2 1 0 mdr mer mda mab mdr monitor channel data receive mer monitor channel end of reception mda monitor channel data acknowledged the remote end has acknowledged the monitor byte being transmitted. mab monitor channel data abort 8.1.31 monitor channel control register mocr read/write address 78h value after reset: 00h 7 6 5 4 3 2 1 0 mrie mrc mxie mxc mrie monitor channel receive interrupt enable monitor channel interrupt status mdr, mer generation is enabled (1) or masked (0). mrc mr bit control determines the value of the mr bit: 0: mr bit always 1. in addition, the mdr interrupt is blocked, except for the first byte of a packet (if mre = 1). 1: mr internally controlled by the W6692 according to monitor channel protocol. in addition, the mdr interrupt is enabled for all received bytes according to the monitor channel protocol (if mre = 1).
W6692 publication release date: october 1998 - 59 - revision a1 mxie monitor channel transmit interrupt enable monitor interrupt status mda, mab generation is enabled (1) or masked (0). mxc mx bit control determines the value of the mx bit: 0: mx always 1. 1: mx internally controlled by the W6692 according to monitor channel protocol. 8.1.32 gci mode control register gcr read/write address 7ch value after reset: 00h 7 6 5 4 3 2 1 0 mac tlp grlp spu pd ge mac monitor transmit channel active (read only) data transmission is in progress in gci mode monitor channel. 0: the previous transmission has been terminated. before starting a transmission, the microprocessor should verify that the transmitter is inactive. 1: after having written data into the monitor transmit channel (mox) register, the microprocessor sets this bit to 1. this enables the mx bit to go active (0), indicating the presence of valid monitor channel data (contents of mox) in the correspond frame. tlp test loop when set this bit to 1 both the dout and din lines are internally connected together, and the constants t1 and t2 in d_timr are reduced. the gci mode loop-back test function: dout is internally connected with din, external input on din is ignored. when tlp = 1 (gci mode test loop-back active): t2 = 16348 * cnt * dcl +t1, with t1 = 512 * (val + 1) * dcl (here: dcl denotes the period of the dcl clock.) grlp gci mode remote loop-back setting this bit to 1 activates the remote loop-back function. the 2b+d channels data received from the gci bus interface are looped to the transmitted channels.
W6692 - 60 - spu software power up pd power down spu pd description 0 1 after u transceiver power down, W6692 will receive the indication dc (deactivation confirmation) from gci bus and then software has to set spu ? 0, pd ? 1 to enter power down state. 1 0 setting spu ? 1, pd ? 0 will pull the gci bus dout line to low. this will enforce connected layer 1 devices (u transceiver) to deliver gci bus clocking. 0 0 after reception of the indication pu (power up indication) the reaction of the microprocessor should be: - to write an ar (activate request command) as c/i command code in the cix register. - to reset the spu bit and wait for the following icc (indication code change) interrupt. 1 1 unused. ge gci mode enable setting this bit to 1 will enable the gci bus interface. in the same time, the s/t layer 1 function is disabled. 8.1.33 peripheral address register xaddr read/write address f4h value after reset : undefined the register content depends on pctl: xmode setting. xmode = 0: simple io mode 7 6 5 4 3 2 1 0 io7 io6 io5 io4 io3 io2 io1 io0 io1-0 read or write data of pins io1-0 input data of pins io1-0 if pctl: oe0 = 0. output data of pins io1-0 if pctl: oe0 = 1. io3-2 read or write data of pins io3-2 input data of pins io3-2 if pctl: oe1 = 0. output data of pins io3-2 if pctl: oe1 = 1. io5-4 read or write data of pins io5-4 input data of pins io5-4 if pctl: oe2 = 0. output data of pins io5-4 if pctl: oe2 = 1.
W6692 publication release date: october 1998 - 61 - revision a1 io7-6 read or write data of pins io3-0 input data of pins io7-6 if pctl: oe3 = 0. output data of pins io7-6 if pctl: oe3 = 1. xmode = 1: 8-bit multiplexed microprocessor mode 7 6 5 4 3 2 1 0 xa7 xa6 xa5 xa4 xa3 xa2 xa1 xa0 xa7-0 peripheral address to access peripheral device, first write the peripheral address in this register and then perform read or write at xdata register. the address written in this register is output on xad7-0 in address phase of data access and can be latched by xale signal. 8.1.34 peripheral data register xdata read/write address f8h value after reset: undefined the register content depends on pctl: xmode setting. xmode = 0: simple io mode 7 6 5 4 3 2 1 0 io10 io9 io8 io9-8 read or write data of pins io9-8 input data of pins io9-8 if pctl: oe4 = 0. output data of pins io9-8 if pctl: oe4 = 1. io10 read or write data of pins io10 input data of pins io10 if pctl: oe5 = 0. output data of pins io10 if pctl: oe5 = 1. xmode = 1: 8-bit multiplexed microprocessor mode 7 6 5 4 3 2 1 0 xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 xd7-0 peripheral data during data phase of peripheral access, they are outputs to xad7-0 if write, or inputs from xad7-0 if read.
W6692 - 62 - 8.1.35 serial eeprom control register epctl write address 68h value after reset: x0h 7 6 5 4 3 2 1 0 en sk cs sdo en enable output 0: disable outputs on pins epsk, epcs, epsdo. 1: enable outputs on pins epsk, epcs, epsdo. sk output data of epsk when enabled, this bit is output on pin epsk. cs output data of epcs when enabled, this bit is output on pin epcs. sdo output data of epsdo when enabled, this bit is output on pin epsdo. 8.2 b1 hdlc controler table 8.3 register address map: b1 channel hdlc section offset access register name description 8.2.1 80 r b1_rfifo b1 channel receive fifo 8.2.2 84 w b1_xfifo b1 channel transmit fifo 8.2.3 88 w b1_cmdr b1 channel command register 8.2.4 8c r/w b1_mode b1 channel mode control 8.2.5 90 r_clear b1_exir b1 channel extended interrupt 8.2.6 94 r/w b1_exim b1 channel extended interrupt mask 8.2.7 98 r b1_star b1 channel status register 8.2.8 9c r/w b1_adm1 b1 channel address mask 1 8.2.9 a0 r/w b1_adm2 b1 channel address mask 2 8.2.10 a4 r/w b1_adr1 b1 channel address 1 8.2.11 a8 r/w b1_adr2 b1 channel address 2 8.2.12 ac r b1_rbcl b1 channel receive frame byte count low 8.2.13 b0 r b1_rbch b1 channel receive frame byte count high
W6692 publication release date: october 1998 - 63 - revision a1 table 8.4 register summary: b1 channel hdlc offset r/w name 7 6 5 4 3 2 1 0 80 r b1_rfifo 84 w b1_xfifo 88 w b1_cmdr rack rrst ract xms xme xrst 8c r/w b1_mode mms itf epcm bsw1 bsw0 sw56 fts1 fts0 90 r_clr b1_exir rmr rme rdov xfr xdun 94 r/w b1_exim rmr rme rdov xfr xdun 98 r b1_star rdov crce rmb xdow xbz 9c r/w b1_adm1 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 a0 r/w b1_adm2 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 a4 r/w b1_adr1 ra17 ra16 ra15 ra14 ra13 ra12 ra11 ra10 a8 r/w b1_adr2 ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 ac r b1_rbcl rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 b0 r b1_rbch lov rbc12 rbc11 rbc10 rbc9 rbc8 8.2.1 b1_ch receive fifo b1_rfifo read address 80h the b1_rfifo is a 128-byte depth fifo memory with programmable threshold. the threshold value determines when to generate an interrupt. when more than a threshold length of data has been received, a rmr interrupt is generated. after an rmr interrupt, 64 or 96 bytes can be read out, depending on the threshold setting. in transparent mode, when the end of frame has been received, a rme interrupt is generated. after an rme interrupt, the number of bytes available is less than or equal to the threshold value. 8.2.2 b1_ch transmit fifo b1_xfifo write address 84h the b1_xfifo is a 128-byte depth fifo with programmable threshold value. the threshold setting is the same as b1_rfifo. when the number of empty locations is equal to or greater than the threshold value, a xfr interrupt is generated. after a xfr interrupt, up to 64 or 96 bytes of data can be written into this fifo for transmission. 8.2.3 b1_ch command register b1_cmdr write address 88h value after reset: 00h 7 6 5 4 3 2 1 0 rack rrst ract xms xme xrst
W6692 - 64 - rack receive message acknowledge after a rmr or rme interrupt, the micro-processor reads out the data in b1_rfifo, it then sets this bit to explicitly acknowledge the interrupt. rrst receiver reset setting this bit resets the b1_ch hdlc receiver. ract receiver active the b1_ch hdlc receiver is active when this bit is set to "1". this bit is write only. the receiver must be in active state in order to receive data. xms transmit message start/continue in transparent mode, setting this bit initiates the transparent transmission of b1_xfifo data. the opening flag is automatically added to the message by the b1_ch hdlc controller. zero bit insertion is performed on the data. this bit is also used in subsequent transmission of the frame. in extended transparent mode, settint this bit activates the transmission of b1_xfifo data. no flag, crc or zero bit insertion is added on the data. xme transmit message end in transparent mode, setting this bit indicates the end of the whole frame transmission. the b1_ch hdlc controller transmits the data in fifo and automatically appends the crc and the closing flag sequence in transparent mode. in extended transparent mode, setting this bit stops the b1_xfifo data transmission. xrst transmitter reset setting this bit resets the b1_ch hdlc transmitter and clears the b1_xfifo. the transmitter will send inter frame time fill pattern on b channel. this command also results in a transmit fifo ready condition. 8.2.4 b1_ch mode register b1_mode read/write address 8ch value after reset: 00h 7 6 5 4 3 2 1 0 mms itf epcm bsw1 bsw0 sw56 fts1 fts0 mms message mode setting determines the message transfer modes of the b1_ch hdlc controller: 0: transparent mode. in receive direction, address comparison is performed on each frame. the frames with matched address are stored in b1_rfifo. flag deletion, crc check and zero bit deletion are performed. in transmit direction, the data is transmitted with flag insertion, zero bit insertion and crc generation. 1: extended transparent mode. in receive direction, all data are received and stored in the b1_rfifo. in transmit direction, all data in the b1_xfifo are transmitted without alteration.
W6692 publication release date: october 1998 - 65 - revision a1 itf inter-frame time fill defines the inter-frame time fill pattern in transparent mode. 0: mark. the binary value "1" is transmitted. 1: flag. this is a sequence of "01111110". epcm enable pcm transmit/receive 0: disable data transmit/ receive to/from pcm port. the frame synchronization clock pfck1 is held low. 1: enable data transmit/ receive to/from pcm port. the frame synchronization clock pfck1 is active. bsw1-0 b channel switching select these two bits determine the connection in b1 channel: bsw1 bsw0 connection 0 0 layer 1 ? hdlc 0 1 layer 1 ? pcm 1 0 hdlc ? pcm 1 1 layer 1 ? pcm, pcm ? hdlc note: the connection with micro-controller is through hdlc controller. when hdlc connects with layer 1, either transparent or extended transparent mode can be used. when hdlc connects with pcm port, only extended transparent mode can be used and the epcm bit must be set to enable pcm function. sw56 switch 56 traffic 0: the data rate in b1 channel is 64 kbps. 1: the data rate in b1 channel is 56 kbps. the most significant bit in each octet is fixed at "1". note: in 56 kbps mode, only transparent mode can be used. fts1-0 fifo threshold select these two bits determine the b1 channel receive and transmit fifo's threshold setting. an interrupt is generated when the number of received data or the number of vacancies in xfifo reaches the threshold value. fts1 fts0 threshold (byte) 0 0 64 0 1 reserved 1 0 96 1 1 not allowed
W6692 - 66 - 8.2.5 b1_ch extended interrupt register b1_exir read_clear address 90h value after reset: 00 h 7 6 5 4 3 2 1 0 rmr rme rdov xfr xdun rmr receive message ready at least a threshold lenth of data has been stored in the b1_rfifo. rme receive message end used in transparent mode only. the last block of a frame has been received. the frame length can be found in b1_rbch + b1_rbcl registers. the number of data available in the b1_rfifo equals frame lenth modulus threshold. the result of crc check is indicated by b1_star:crce bit. when the number of last block of a frame equals the threshold, only rme interrupt is generated. rdov receive data overflow data overflow occurs in the receive fifo. the incoming data will overwrite the data in the receive fifo. xfr transmit fifo ready this interrupt indicates that up to a threshold length of data can be written into the b1_xfifo. xdun transmit data underrun this interrupt occurs when the b1_xfifo has run out of data. in this case, the W6692 will automatically reset the transmitter and send the inter frame time fill pattern on b channel. the software must wait until transmit fifo ready condition (via xfr interrupt), re-write data, and issue xms command to re-transmit the data. 8.2.6 b1_ch extended interrupt mask register b1_exim r ead/write address 94h value after reset: ffh 7 6 5 4 3 2 1 0 rmr rme rdov xfr xdun setting the bit to "1" masks the corresponding interrupt source in b1_exir register. masked interrupt status bits are read as zero when b1_exir register is read. they are internally stored and pending until the mask bits are zero. all the interrupts in b1_exir will be masked if the imask: b1_exi bit is set to "1". 8.2.7 b1_ch status register b1_star read address 98h value after reset: 20h 7 6 5 4 3 2 1 0 rdov crce rmb xdow xbz
W6692 publication release date: october 1998 - 67 - revision a1 rdov receive data overflow a "1" indicates that the d_rfifo is overflow. the incoming data will overwrite data in the receive fifo. the overflow condition will set both the status and interrupt bits. it is recommended that software must read the rdov bit after reading data from d_rfifo at rmr or rme interrupt. the software must abort the data and issue a rrst command to reset the receiver if rdov = 1. crce crc error used in transparent mode only. this bit indicates the result of frame crc check: 0: crc correct 1: crc incorrect rmb receive message aborted used in transparent mode only. a "1" means that a sequence of 3 seven 1's was received and the frame is aborted by the b1_hdlc receiver. software must issue rrst command to reset the receiver. note: bits crce and rmb are valid only after a rme interrupt and remain valid until the frame is acknowledged via rack command xdow transmit data overwritten at least one byte of data has been overwritten in the b1_xfifo. this bit is cleared only by xrst command. xbz transmitter busy the b1_hdlc transmitter is busy when xbz is read as "1". this bit may be polled. the xbz bit is active when an xms command was issued and the message has not been completely transmitted. 8.2.8 b1_ch address mask register 1 b1_adm1 read/write address 9ch value after reset : 00h 7 6 5 4 3 2 1 0 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 ma17-10 address mask bits used in transparent mode only. these bits mask the first byte address comparisons. if the mask bit is "1", the corresponding bit comparison with b1_adr1 is disabled. 0: unmask comparison 1: mask comparison 8.2.9 b1_ch address mask register 2 b1_adm2 read/write address a0h value after reset: 00h 7 6 5 4 3 2 1 0 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20
W6692 - 68 - ma27-20 address mask bits used in transparent mode only. these bits mask the second byte address comparisons. if the mask bit is "1", the corresponding bit comparison with b1_adr2 is disabled. 0: unmask comparison 1: mask comparison 8.2.10 b1_ch address register 1 b1_adr1 read/write address a4h value after reset: 00h 7 6 5 4 3 2 1 0 ra17 ra16 ra15 ra14 ra13 ra12 ra11 ra10 ra17-10 address bits used in transparent mode only. these bits are used for the first byte address comparisons. 8.2.11 b1_ch address register 2 b1_adr2 read/write address a8h value after reset: 00h 7 6 5 4 3 2 1 0 ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 ra27-20 address bits used in transparent mode only. these bits are used for the second byte address comparisons. 8.2.12 b1_ch receive frame byte count low b1_rbcl read address ach value after reset: 00h 7 6 5 4 3 2 1 0 rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 rbc7-0 receive byte count used in transparent mode only. eight least significant bits of the total number of bytes in a received frame. these bits are valid only after a rme interrupt and remain valid until the frame is acknowledge via the rack bit. 8.2.13 b1_ch receive frame byte count high b1_rbch read address b0h value after reset: 00h 7 6 5 4 3 2 1 0 lov rbc12 rbc11 rbc10 rbc9 rbc8
W6692 publication release date: october 1998 - 69 - revision a1 lov message length overflow used in transparent mode only. a "1" in this bit indicates a received message 3 4097 bytes. this bit is valid only after rme interrupt and is cleared by the rack command. rbc12-8 receive byte count used in transparent mode only. five most significant bits of the total number of bytes in a received frame. these bits are valid only after a rme interrupt and remain valid until the frame is acknowledge via the rack bit. note: the frame length equals rbc12-0. this length is between 1 to 4096. after a rme interrupt, the number of data available in b1_rfifo is frame length modulus threshold. remainder = rbc12-0 mod threshold no. of available data = remainder if remainder 1 0 or no. of available data = threshold if remainder = 0 the remainder equals rbc5-0 if threshold is 64. 8.3 b2 hdlc controller table 8.5 register address map: b2 channel hdlc offset access register name description c0 r b2_rfifo b2 channel receive fifo c4 w b2_xfifo b2 channel transmit fifo c8 w b2_cmdr b2 channel command register cc r/w b2_mode b2 channel mode control d0 r_clear b2_exir b2 channel extended interrupt d4 r/w b2_exim b2 channel extended interrupt mask d8 r b2_star b2 channel status register dc r/w b2_adm1 b2 channel address mask 1 e0 r/w b2_adm2 b2 channel address mask 2 e4 r/w b2_adr1 b2 channel address 1 e8 r/w b2_adr2 b2 channel address 2 ec r b2_rbcl b2 channel receive frame byte count low f0 r b2_rbch b2 channel receive frame byte count high
W6692 - 70 - table 8.6 register summary: b2 channel hdlc offset r/w name 7 6 5 4 3 2 1 0 c0 r b2_rfifo c4 w b2_xfifo c8 w b2_cmdr rack rrst ract xms xme xrst cc r/w b2_mode mms itf epcm bsw1 bsw0 sw56 fts1 fts0 d0 r_clr b2_exir rmr rme rdov xfr xdun d4 r/w b2_exim rmr rme rdov xfr xdun d8 r b2_star rdov crce rmb xdow xbz dc r/w b2_adm1 ma17 ma16 ma15 ma14 ma13 ma12 ma11 ma10 e0 r/w b2_adm2 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 e4 r/w b2_adr1 ra17 ra16 ra15 ra14 ra13 ra12 ra11 ra10 e8 r/w b2_adr2 ra27 ra26 ra25 ra24 ra23 ra22 ra21 ra20 ec r b2_rbcl rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 f0 r b2_rbch lov rbc12 rbc11 rbc10 rbc9 rbc8 the b2 channel hdlc register's definitions and functions are the same as those of b1 channel hdlc. please refer to section 8.2 for a detailed description. 8.4 pci configuration register W6692 provides pci interface for pci-base system and only supports slave mode. there are two optional base address registers (memory or i/o) for host access to W6692 internal registers. reads to reserved or unimplemented registers return data value of 0. write to these registers are completed normally and the data are discarded. after power on reset, W6692 automatically reads the configuration data from serial eeprom interface. the first word read is vendor id. if vendor id = ffff h , W6692 assumes eeprom is empty and will use built-in default configuration data., otherwise, configuration data from eeprom is used. please refer to section 7.9.1 for serial eeprom data format.
W6692 publication release date: october 1998 - 71 - revision a1 table 8.7 pci configuration space address\bit 31 24 23 16 15 8 7 0 00 h device id vendor id 04 h status command 08 h class code revision id 0c h -- header type -- 10 h base address register 0 14 h base address register 1 18 h - 28 h not implemented. read as 0. 2c h subsystem id subsystem vendor id 30 h - 38 h not implemented. read as 0. 3c h -- -- interrupt pin interrupt line 8.4.1 device/vendor id register read address 00 h pci configuration address: 00 h default: 6692 1050 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 device id 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vendor id bits 31-16 device id device id is loaded from eeprom after power on reset, if eeprom is not empty. device id is winbond s device id: 6692 h , if eeprom is empty. bits 15-0 vendor id vendor id is allocated by the pci sig to ensure uniqueness. the value is loaded from eeprom after power on reset , if eeprom is not empty. vendor id is winbond s vendor id: 1050 h , if eeprom is empty. 8.4.2 status/command register read/write address 04 h pci configuration address: 04 h default: 0200 0000 h
W6692 - 72 - 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dp e -- -- -- sta devsel -- fbt ud f 66m -- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -- -- -- -- pee -- mae io ae bits 31-16 are status register and bits 15-0 are command register. reads to status register behave normally. bits in status register are cleared if the corresponding write data bits are '1' in a write operation. bits 15-0 are command register. when 00 h is written to this register, the device is logically disconnected from the pci bus for all accesses except configuration accesses. the power up value of command register is 00 h. bit 31 dpe detected parity error r/w_clr 1 = a parity error is detected. 0 = no parity error is detected. bit 30 sse signaled system error not implemented. read as 0. bits 29-28 master aborted, target aborted not implemented. read as 0. bit 27 sta signaled target abort r/w_clr 1 = target abort is signalled. 0 = target abort is not signalled. bits 26-25 devsel timing read_only 01 = medium devsel# timing. bits 24 perr# asserted not implemented. read as 0. bit 23 fbt fast back-to-back transaction read_only 0 = unable to accept fast back-to-back transaction. bit 22 udf user definable features read_only 0 = unable to support user definable features. bit 21 66m 66 mhz function read_only 0 = support 33 mhz only.
W6692 publication release date: october 1998 - 73 - revision a1 bits 20-16 reserved read as 0 bits 15-10 reserved read as 0 bits 9 fast back-to-back not implemented. read as 0. bit 8 see serr# driver enable not implemented. read as 0. bits 7 address/data stepping not implemented. read as 0 bit 6 pee parity error response enable r/w 1 = enable parity error response 0 = disable parity error response bits 5-2 vga palette, memory write and invalidate, special cycle not implemented. read as 0. bit 1 mae memory access enable r/w 1 = enable memory access response 0 = disable memory access response bit 0 ioae i/o access enable r/w 1 = enable i/o access response 0 = disable i/o access response 8.4.3 class code/revision id register read address 08 h pci configuration address: 08 h default: 0280 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 base class code sub-class code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 programming interface revision id bits 31-8 class code read_only this value is loaded from eeprom after power on reset, if eeprom is not empty.
W6692 - 74 - the default value is 028000 h to specify that the W6692 is an isdn network communication device , if eeprom is empty. bits 7-0 revision id read_only this value is assigned by the isdn system manufacturer and identifies the revision number of the system. this value is loaded from eeprom after power on reset, if eeprom is not empty. the default value is 00 h, if eeprom is empty. 8.4.4 header type/latency timer register read address 0c h pci configuration address: 0c h default: 0000 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bist header type 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 latency timer cache line size bits 31-24 bist built-in self test read_only this register is always read as 0. it means that W6692 does not support bist function. bits 23-16 header type read_only the value of this register is 00 h . this means a signle function device, with header type 00 h . bits 15-8 latency timer read_only this register is not implemented and is read as 0. bits 7-0 cache line size read_only this register is not implemented and is read as 0. 8.4.5 base address register 0 read/write address 10 h depending on eeprom status and men, ien bits in eeprom, there are different implementations: men ien location 10h location 14h pre used 1 1 memory base address reg. io base address reg. yes 1 0 memory base address reg. not implemented yes 0 1 io base address reg. not implemented no 0 0 not implemented not implemented no eeprom empty memory base address reg. io base address reg. pre = 1
W6692 publication release date: october 1998 - 75 - revision a1 if eeprom is empty, the power on reset value at 10 h = 0000 0008 h , and the power on reset value at 14 h = 0000 0001 h memory base adress register: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 memory base address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 memory base address hardwired to 0 pre type 0 this register can be used to relocate memory address space to any location that is aligned to 4k bytes for mapping W6692's internal registers. bits 31-12 memory base address r/w these bits are read/write and are used to relocate the memory address space at 4k byte boundary. bits 11-4 read_only these bits are read_only and are hardwired to 0 . bit 3 prefetchable read_only this bit is hardwred to 1, if eeprom is empty, otherwise, it is loaded from eeprom. bits 2-1 type read_only these two bits are hardwired to 00, indicating the memory range can locate anywhere in 32 bit address space. bit 0 memory space indicator read_only this bit is hardwired to 0, indicating a memory space is allocated. io base address register: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 i/o base address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i/o base address hardwired to 0 0 1 this register can be used to relocate i/o address space to any location that is aligned to 256 bytes for mapping W6692's internal registers.
W6692 - 76 - bits 31-8 io base address r/w these bits are read/write and are used to relocate the io address space at 256 byte boundary. bits 7-2 read_only these bits are read_only and are hardwired to 0 . bit 1 reserved read_only this bit is reserved and is hardwired to 0. bit 0 io space indicator read_only this bit is hardwired to 1, indicating a i/o space is allocated. 8.4.6 base address register 1 read/write address 14 h see the above section. 8.4.7 subsystem/subsystem vendor id register read address 2c h pci configuration address: 2c h default: ffff ffff h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 subsystem id 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 subsystem vendor id bits 31-16 subsystem id read_only subsystem id is loaded from eeprom after power on reset, if eeprom is not empty. the default value is ffff h, if eeprom is empty. bits 15-0 subsystem vendor id read_only subsystem vendor id is assigned by the manufacturer to ensure uniqueness. the value is loaded from eeprom after power on reset , if eeprom is not empty. the default value is ffff h, if eeprom is empty.
W6692 publication release date: october 1998 - 77 - revision a1 8.4.8 interrupt line register read/write address 3c h pci configuration address: 3c h default: 0000 0100 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 max_latency timer min_gnt timer 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 interrupt pin interrupt line bits 31-24 max_latency timer read_only this register is hardwired to 0, indicating no major requirements for the settings of latency timers. bits 23-16 min_gnt timer read_only this register is hardwired to 0. bits 15-8 interrupt pin read_only this register is hardwired to 01 h to specify that inta# is the interrupt pin used. bits 7-0 interrupt line r/w this 8-bit register is used to communicate interrupt line routing information. power on self test (post) software must write the routing information into this register as it initializes and configures the system. 9. electrical characteristics 9.1 absolute maximum rating parameter symbol limit values unit voltage on any pin with respect to ground v s -0.4 to v dd +0.4 v ambient temperature under bias t a 0 to 70 c maximum voltage on v dd v dd 6 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device.
W6692 - 78 - 9.2 power supply the power supply is 5v 5%. 9.3 dc characteristics t a = 0 to 70 c; v dd = 5v 5%, v ssa = 0v, v ssd = 0v parameter sym. min. max. unit test conditions remarks low input voltage v il -0.4 0.8 v high input voltage v ih 2.0 v dd +0.4 v low output voltage v ol 0.4 v i ol = 12 ma high output voltage v oh 2.4 v power supply current: power down i cc 4.0 ma v dd = 5v, inputs at v dd /v ss , no output loads except at sx1, 2 (50 w load) power supply current: operational i cc 17 ma v dd = 5v, inputs at v dd /v ss , no output loads except at sx1, 2 (50 w load) input leakage current i li 10 m a 0v < v in < v dd to 0v all pins except sx1, 2, sr1, 2 output leakage current i lo 10 m a 0 v < v out < v dd to 0v all pins except sx1, 2, sr1, 2 absolute value of output pulse amplitude (v sx2 -v sx1 ) v x 2.03 2.10 2.31 2.39 v v r l = 50 w 1) r l = 400 w 1) sx1, 2 transmitter output current i x 7.5 13.4 ma r l = 5.6 w 1) sx1, 2 transmitter output impedence r x 30 23 k w w inactive or during binary one during binary zero (r l = 50 w ) sx1, 2 note: 1) due to the transformer, the load resistance seen by the circuit is four times r l .
W6692 publication release date: october 1998 - 79 - revision a1 capacitances t a = 25 c, v dd = 5v 5%, v ssa = 0v, v ssd = 0v, fc = 1 mhz, unmeasured pins grounded. parameter symbol min. max. unit remarks input capacitance c in 7 pf all pins except sr1, 2 i/o pin capacitance c io 7 pf all pins except sr1, 2 output capacitance against v ssa c out 10 pf sx1, 2 input capacitance c in 7 pf sr1, 2 load capacitance c l 50 pf xtal1, 2 recommended oscillator circuits crystal specifications parameter symbol values unit frequency f 7.680 mhz frequency calibration tolerance max. 100 ppm load capacitance c l max. 50 pf oscillator mode fundamental note: the load capacitance c l depends on the crystal specification. the typical values are 33 to 47 pf. external ocsillator input (xtal1) clock characteristics parameter min. max. duty cycle 1:2 2:1 50 xtal1 xtal2 51 7.68 mhz c l 50 pf c l c l 50 xtal1 xtal2 51 external oscillator signal n.c. or
W6692 - 80 - 9.4 preliminary switching characteristics 9.4.1 pcm interface timing notes: 1. these drawings are not to scale. 2: the frequency of pbck is 1536 khz which includes 24 channels of 64 kbps data. the pfck1 and pfck2 are located at channel 1 and channel 13, each with a 8 x pbck duration. detailed pcm timing pbck pfck1 pfck2 ptxd prxd ta1 ta2 ta3 ta4 ta5 ta6 ta7 ta8 pbck 2) (1.536 mhz) pfck1 2) pfck2 2) ptxd prxd 24 chs ch 1 ch 13 port port port port port port
W6692 publication release date: october 1998 - 81 - revision a1 parameter parameter descriptions min. max. remarks ta1 pbck pulse high 260 unit = ns ta2 pbck pulse low 260 ta3 frame clock asserted from pbck 20 ta4 ptxd data delay from pbck 20 ta5 frame clock deasserted from pbck 20 ta6 ptxd hold time from pbck 10 ta7 prxd setup time to pbck 20 ta8 prxd hold time from pbck 10 9.4.2 serial eeprom timing parameter parameter descriptions min. max. remarks tb1 epsk low 2500 unit = ns tb2 epsk high 2500 tb3 epcs output delay 30 tb4 epsd output delay 30 tb5 epsd tri-state delay 30 tb6 epsd input setup time 30 tb7 epsd input hold time 30 a5 a4 a1 a0 ..... d15 d14 d1 d0 ....... tb1 tb2 tb3 tb3 tb4 tb4 tb5 tb7 tb6 epsk epcs epsdi
W6692 - 82 - 9.4.3 peripheral interface timing 8-bit microprocessor timing when xmode = 1: xale pci clk xad7-0 xwrb peripheral write tc1 tc2 tc3 tc5 tc4 hi-z hi-z hi-z hi-z hi-z hi-z xale pci clk xad7-0 xrdb peripheral read tc1 tc2 tc7 tc8 tc6 hi-z hi-z hi-z hi-z hi-z hi-z parameter parameter descriptions min. max. typical remarks tc1 xa7-0 setup time 30 unit = ns tc2 xa7-0 hold time 30 tc3 xwrb pulse width 90 tc4 write data setup time 90 tc5 write data hold time 30 tc6 xrdb pulse width 120 tc7 read data delay time 90 tc8 read data hold time 0
W6692 publication release date: october 1998 - 83 - revision a1 9.5 ac timing test conditions (t a = 0 to 70 c, v dd = 5v 5%) inputs are driven to 2.4v for logical 1 and 0.4v for logical 0. measurements are made at 2.0v for logical 1 and 0.8v for logical 0. the ac testing input/output waveforms are shown below: 10. package dimensions 100l qfp (14 20 2.75 mm footprint 4.8 mm) e h y a a2 seating plane l l 1 see detail f 0.08 0 7 0 0.003 2.40 1.40 19.20 1.20 18.80 1.00 18.40 0.064 0.055 0.992 0.756 0.047 0.976 0.740 0.039 0.960 0.746 0.65 20.10 14.10 0.20 0.40 2.87 20.00 14.00 2.72 19.90 13.90 0.10 0.20 2.57 0.791 0.555 0.008 0.016 0.113 0.787 0.551 0.107 0.026 0.783 0.547 0.004 0.008 0.101 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.012 0.006 0.15 0.30 24.40 24.80 25.20 7 0.020 0.032 0.498 0.802 0.35 0.25 0.010 0.014 0.018 0.45 q q controlling dimension : millimeters a1 e d h d e b c test point 2.0 0.8 2.0 0.8 2.4 0.4 device under test c load = 150 pf
W6692 - 84 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792646 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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